Xunyuan Zhang

BEOL process integration for the 7 nm technology node

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

Ruthenium interconnect resistivity and reliability at 48 nm pitch

48 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Ru interconnect has comparable high yield for line and via macros. Electrical results show minimal impact for via resistance and around 2 times higher line resistance. Resistivity and cross section area of Ru interconnects are measured by temperature coefficient of resistivity method and the area was verified by TEM. Reliability results show non-failure in electromigration and longer time dependent dielectric breakdown. Based on the data collected, Ru could be a metallization contender at linewidth of 16 nm and below.

CVD-Co/Cu(Mn) integration and reliability for 10 nm node

In studying integrated dual damascene hardware at 10 nm node dimensions, we identified the mechanism for Co liner enhancement of Cu gap-fill to be a wetting improvement of the PVD Cu seed, rather than a local nucleation enhancement for Cu plating. We then show that Co “divot” (top-comer slit void defect) formation can be suppressed by a new wet chemistry, in turn eliminating divot-induced EM degradation. Further, we confirm a relative decrease in Cu-alloy seed proportional resistivity impact compared to scattering at scaled dimensions, and finally we address the incompatibility between the commonly-used carbonyl-based CVD-Co process with Cu-alloy seed EM performance This problem is due to oxidation of Ta(N) barriers at the TaN/CVD-Co interface by carbonyl-based CVD processes, which then consumes alloy atoms before they can segregate at the Cu/cap interface. We show that O-free CVD-Co may solve this problem. The above solutions may then enable CVD-Co/Cu-alloy seed integration in advanced nodes.

Performance of ultrathin alternative diffusion barrier metals for next - Generation BEOL technologies, and their effects on reliability

In order to maximize Cu volume and reduce via resistance, barrier thickness reduction is a strong option. Alternative barriers for next-generation BEOL were evaluated in terms of barrier performance to O2 and Cu diffusion, and effects on reliability. A clear correlation of O2 barrier performance to electromigration was observed, suggesting that the key role of the barrier layer is to prevent oxidation of Cu or the Cu/barrier interface. Long-throw PVD-TaN showed superior O2 barrier performance to alternative metals such as PEALD-TaN, thermal ALD-TaN, -TaN(Mn) and - MnN and MnSiO3 self-forming barrier.

Middle of line RC performance study at the 7 nm node

In this paper, a study on MOL (middle-of-the-line) RC performance and optimization of MOL resistance at both source/drain contact and local interconnect level at 7 nm node is presented. We focus on the device delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on a real 10 nm FINFET device. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, using this model the impact of the MOL on the circuit performance can be determined. By using a liner-free W (tungsten) metallization at source drain contact level and Co (cobalt) or Ru (ruthenium) metallization in the MOL local interconnect level, a 45% reduction in MOL resistance was obtained which is crucial to achieve a better 7 nm MOL performance over the 10 nm node.

Cobalt interconnect on same copper barrier process integration at the 7nm node

Cobalt and copper interconnects with identical barrier and CMP processes were formed on ultra-low k (ULK) dielectric films at the 7nm node. Divot-free Co and Cu interconnects are demonstrated using the same CMP process. Co-filled dual damascene interconnects show high line yields with similar via resistance values compared to Cu. Co line resistance measures three times higher resistance than Cu. The resistivity of Co and Cu lines is calculated by measuring line resistance and cross-sectional area by transmission electron microscopy (TEM). Measured via resistance of the dual damascene Co-filled via is only 10% higher than the Cu-filled via control. Thus by scaling or even eliminating traditional Cu barriers in the via, Co can be a valid Cu replacement candidate for via fill.

Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires

Electromigration and resistivity of Cu, Co and Ru on-chip interconnection have been investigated. A similar resistivity size effect increase was observed in Cu, Co, and Ru. The effect of liners and cap, e.g. Ta, Co, Ru and SiCxNyHz, on Cu/interface resistivity was not found to be significant. Multilevel Cu, Co or Ru back-end-of-line interconnects were fabricated using 10 nm node technology wafer processing steps. EM in 22 nm to 88 nm wide Co lines, 24 nm wide Cu with and without a thin Co cap and 24 nm wide Ru lines were tested. These data showed that Cu with a Co cap, Co and Ru had highly reliable EM, although Ru was better than Co and Co was better Cu. The electromigration activation energies for Cu with Co cap and Co were found to be 1.5–1.6 eV and 2.1–2.7 eV, respectively.

Methods to lower the resistivity of ruthenium interconnects at 7 nm node and beyond

36 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Different adhesion layers are used to form the Ru interconnects. Ru line resistivity is measured by the temperature coefficient of resistivity method, and the area verified by TEM. Ru line resistivity is found to depend on the adhesion layer. The adhesion layers with higher intrinsic resistivities reduced the Ru line resistivity. A ∼10% Ru resistivity reduction can be achieved with ALD TaN or TiN adhesion layers or oxidized TaN, relative to PVD TaN. Grain boundary scattering may play an additional role, as demonstrated by different aspect ratio samples. The lowest Ru resistivity in these interconnects is 15 µΩ-cm, at a cross-sectional area of 300 nm2. Ru damascene metallization is extendible to features with critical dimension around 10 nm. Ru may match Cu line resistance for line dimensions below ∼17 nm.

BEOL challenges for 14nm node and beyond

Scaling the BEOL into 14nm includes challenges in both the material selection and the integration. Metallization-induced degradation of the ULK is an issue regardless of dielectric choice, or the PVD vs. ALD selection, and options for possible recovery of characteristics are numerous. In barrier/liner/seed decisions, the integration choices play into material selection, and the deposition techniques impact upon microstructure, and hence reliability, is significant. For plating, conventional processes may not allow the high fill speeds necessary, and aspect ratio constraints are driving processes to new areas. Finally, we will also address how CPI is changing as interconnect evolves.

Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.