Y. You

LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade

In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-μm Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.

8-Gbps-per-channel radiation-tolerant VCSEL drivers for the LHC detector upgrade

We present ASIC designs of VCSEL drivers for a single VCSEL (LOCld1), two individual VCSELs (LOCld2) and a four-channel VCSEL array (LOCld4). This work is for new detector readout systems needed in the Large Hadron Collider upgrade program. All ASICs are fabricated in a commercial 0.25-μ m Silicon-on-Sapphire CMOS technology. LOCld1 and LOCld2 have passed the 8-Gbps and 10-Gbps eye mask tests. Operating at 8 Gbps data rate, the measured total jitter of LOCld1 and LOCld2 is less than 30 ps, and the power comsuption is about 200 mW per channel with 6-mA bias current and 6.4-mA modulation current. The radiation tolerance of LOCld1 has been qualified with x-ray and high-energy neutron beam test.

A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments

We propose a line code that has fast resynchronization capability and low latency. Both the encoder and decoder have been implemented in FPGAs. The encoder has also been implemented in an ASIC. The latency of the whole optical link (not including the optical fiber) is estimated to be less than 73.9 ns. In the case of radiation-induced link synchronization loss, the decoder can recover the synchronization in 25 ns. The line code will be used in the ATLAS liquid argon calorimeter Phase-I trigger upgrade and can also be potentially used in other LHC experiments.

Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments.

The clock and control system for the ATLAS Liquid Argon Calorimeter Phase-I upgrade

A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to upgrade the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system is being developed for the LTDB and the major functions of the system have been evaluated. The design and evaluation of the clock and control system are presented in this paper.

The VCSEL-based array optical transmitter (ATx) development towards 120-Gbps link for collider detector: development update

A compact radiation-tolerant array optical transmitter module (ATx) is developed to provide data transmission up to 10Gbps per channel with 12 parallel channels for collider detector applications. The ATx integrates a Vertical Cavity Surface-Emitting Laser (VCSEL) array and driver circuitry for electrical to optical conversion, an edge warp substrate for the electrical interface and a micro-lens array for the optical interface. This paper reports the continuing development of the ATx custom package. A simple, high-accuracy and reliable active-alignment method for the optical coupling is introduced. The radiation-resistance of the optoelectronic components is evaluated and the inclusion of a custom-designed array driver is discussed.

Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.

Wireless Networking Testbed and Emulator (WiNeTestEr)

Repeatability, isolation and accuracy are the most desired factors while testing wireless devices. However, they cannot be guaranteed by traditional drive tests. Channel emulators play a major role in filling these gaps in testing. In this paper we present an efficient channel emulator which is better than existing commercial products in terms of cost, remote access, support for complex network topologies and scalability. We present the hardware and software architecture of our channel emulator and describe the experiments we conducted to evaluate its performance against a commercial channel emulator.

SET Detection and Compensation and Its Application in PLL Design

This paper presents a new charge compensation (CC) scheme to mitigate single event transient (SET) effect at the output node of the charge pump (CP), the most SET vulnerable node in a Phase-Locked Loop (PLL). It achieves a 4X less SET-induced voltage disturbance at the ring oscillator control node as well as a faster PLL recovery time. During the normal operation, the CC circuit does not affect the PLL dynamics. Its control block ensures that the CC circuit is enabled only when the CP output voltage is disturbed by SET strikes. This avoids the conflict between SET charge compensation and normal PLL phase correction. The PLL covers a 12.5 MHz to 500 MHz tuning range with a root-mean-square (RMS) jitter of 4.9 ps. It consumes 21.5 mW of power under a 1.5 V power supply. The CC circuit consumes 4.5 mW power and occupies 5.3% of the PLL area.

The clock distribution system for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade Demonstrator

A prototype Liquid-argon Trigger Digitizer Board (LTDB), called the LTDB Demonstrator, has been developed to demonstrate the functions of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. Forty Analog-to-Digital converters and four FPGAs with embedded multi-gigabit-transceivers on each Demonstrator need high quality clocks. A clock distribution system based on commercial components has been developed for the Demonstrator. The design of the clock distribution system is presented. The performance of the clock distribution system has been evaluated. The components used in the clock distribution system have been qualified to meet radiation tolerance requirements of the Demonstrator.