Yuan Du

A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface

This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace. With differential current-mode signaling, the transceiver consumes only 5.4 mW and takes only 80×100 μm2. A real-time flexible BER testing platform is established to prove that the BER of the transceiver is less than 1012.

A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS

A current-mode 60-GHz direct-conversion receiver, which can break performance tradeoffs among bandwidth, noise figure (NF), and linearity is designed and realized in 65-nm CMOS. The 60-GHz receiver employs the novel frequency-staggered series resonance common source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receivers current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature local oscillator generations, the fabricated receiver simultaneously achieves minimal NF of 3.8 dB, RF bandwidth of 7.5 GHz, output P1 dB of 1 dBm, and maximum conversion gain of 36 dB. The receiver is capable of tolerating out-of-channel blocker up to -9 dBm at 3.5 GHz away. It occupies a silicon area of 1.3 mm2 and draws 25.5 mA of current from a 1-V supply.

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection

A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4

A wide-band 65nm CMOS 28–34 GHz synthesizer module enabling low power heterodyne spectrometers for planetary exploration

\mu \text{W}

10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface

/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.

A Current-Mode mm-Wave direct-conversion receiver with 7.5GHz Bandwidth, 3.8dB minimum noise-figure and +1dBm P 1dB, out linearity for high data rate communications

This paper presents a wide-band 28-34 GHz frequency synthesizer module developed to support THz spectrometer instruments for planetary exploration. The presented module features low power operation and a small form factor to be compatible with the demanding payload requirements of NASA planetary missions. The core of the module is a CMOS System-on-Chip (SoC) containing a sub-sampled phase-detector (SSPD) based phase lock-loop, power amplifier, power sensor and digital calibration. The demonstrated module draws a total of 81.2 mW of power from a USB connection and provides coverage from 28-34 GHz with output powers better than -4.0 dBm across the entire band. The offered mid-band phase noise is measured at -96.6 dBc/Hz evaluated at 1 MHz offset from the carrier.

A Capacitor-DAC-Based Technique For Pre-Emphasis-Enabled Multilevel Transmitters

The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]-[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized double-sideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.

A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

A current-mode mm-wave direct-conversion receiver breaking trade-offs among bandwidth, NF and linearity is designed and realized in 65nm CMOS. The 60GHz receiver employs novel Frequency-staggered Series Resonance Common Source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receivers current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature LO generations, the fabricated receiver simultaneously achieves minimal noise figure of 3.8dB, RF bandwidth of 7.5GHz, output P1dB of 1dBm, maximum conversion gain of 32dB, and IRR of -35dB. The receiver is capable of tolerating outof-channel blocker up to -9dBm at 3.5GHz away. It occupies silicon area of 1.3mm2 and draws 25.5mA from 1V supply.

Hybrid thermal aware reconfigurable 3D IC with dynamic power gating architecture

This brief presents a capacitor digital-to-analog converter (DAC) based technique that is suitable for pre-emphasis-enabled multilevel wireline transmitter design in voltage mode. Detailed comparisons between the proposed technique and conventional direct-coupling-based as well as resistor-DAC-based multilevel transmitter design techniques are given, revealing potential benefits in terms of speed, linearity, implementation complexity, and also power consumption. A PAM-4 transmitter with 2-Tap feed-forward equalization adopting the proposed technique is implemented in 65-nm CMOS technology. It achieves a 25-Gb/s data rate and energy efficiency of 2 mW/Gb/s.

A spectral profiling method of mm-wave and terahertz radiation sources

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution window size. In addition, max-pooling function can be computed in parallel with convolution by using separate pooling unit, thus achieving throughput improvement. A prototype accelerator was implemented in TSMC 65-nm technology with a core size of 5 mm2. The accelerator can support major CNNs and achieve 152GOPS peak throughput and 434GOPS/W energy efficiency at 350 mW, making it a promising hardware accelerator for intelligent IoT devices.