Yann Civale

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.

Selective Solid-Phase Silicon Epitaxy of

A solid-phase epitaxy (SPE) process based on material inversion of an amorphous silicon (alpha-Si) on aluminum layer-stack is applied to form ultrashallow p-type junctions. In this paper, we demonstrate the controllability of the whole process when the junction area is reduced to the sub-100-nm range and the processing temperature is reduced to 400 degC. The SPE-Si to Si-substrate interface, analyzed locally by transmission electron microscopy and more systematically by the fabrication and electrical characterization of p+-n diodes, was found to be practically defect-free. Moreover, it is demonstrated by capacitance-voltage profiling that the Al-dopants do not diffuse into the bulk silicon for the used processing temperatures and the SPE p+-island to n-substrate transition is ideally abrupt. The I-V characteristics of the as-fabricated p+-n diodes are near ideal (n=1.03) and low-ohmic contact resistance to p- and p + regions is reliably obtained

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A procedure has been implemented for a quantitative aluminum-doping profiling of µm-scale aluminum-induced solid-phase-epitaxy (SPE) Si islands formed at 400°C. The aluminum concentration was measured to be 1–2×1019 cm?3, which is about 10 times higher than previously reported electrical activation levels. The elemental concentration was measured by secondary-ion-mass-spectroscopy (SIMS) on arrays of SPE Si islands grown by a recently developed process that allows control of the island geometry.

Aluminum-Doped Contacts for Nanoscale Devices

This paper reviews several novel process modules developed for the processing of the backside of the wafer of our substrate-transfer technology called back-wafer-contacted silicon-on-glass (SOG), which is in use for fabricating RF/microwave devices such as high-quality varactors and bipolar transistors. In this technology the silicon wafer is transferred to glass by gluing. The integrity of the acrylic adhesive limits the subsequent processing temperatures to less than 300°C. Ultra-low-temperature process modules have therefore been developed to nevertheless allow the creation of low-ohmic contacts and high-quality ultrashallow junctions. Moreover, a physical-vapor deposition of AlN provides an effective means of integrating a thin-film dielectric heatspreader.

Accurate SIMS Doping Profiling of Aluminum-Doped Solid-Phase Epitaxy Silicon Islands

This work focuses on FinFETs with high aspect-ratio and thus a wide MOSFET channels in each fin, which translates into higher device density per chip area and more efficient use of the silicon real-estate. Moreover, in analog applications where multi-fin devices are required for wider transistors, a small number of taller fins is preferable to a large number of shorter fins in terms of gate resistance and gate capacitance which improves high-frequency performance. The fabrication process is designed to keep the fin-width in the 10 nm range while at the same time tall fins are etched.

Ultra-low-temperature process modules for back-wafer-contacted silicon-on-glass RF/microwave technology

A solid phase epitaxy (SPE) technique was developed to grow p + aluminum-doped crystalline Si in a fully CMOS compatible process. This paper describes the experimental conditions leading to the selective growth of nanoscale single crystals where the location and dimensions are well controlled, even in the sub-100 nm range. The SPE Si crystals are defined by conventional lithography and show excellent electrical characteristics. Fifty-nanometer-thick p + SPE Si crystals were used to fabricate p + -n-p bipolar junction transistors. The remarkable control of the whole process, even in the sub-100 nm range, make this module directly usable for Si-based nanodevices.

1.9 nm wide ultra-high aspect-ratio bulk-Si FinFETs

A solid-phase epitaxy (SPE) process that forms ultra-shallow abrupt aluminum p+-doped Si islands has been studied for deposition temperatures from 400 to 500 oC. The growth process gives a very uniform composition of the p+ layer and an abrupt doping transition to the Si substrate. Low ohmic contacting and near-ideal diode characteristics are reliably obtained.