Vladimir Jovanović

SiGe growth on patterned Si(001) substrates: Surface evolution and evidence of modified island coarsening

The morphological evolution of both pits and SiGe islands on patterned Si(001) substrates is investigated. With increasing Si buffer layer thickness the patterned holes transform into multifaceted pits before evolving into inverted truncated pyramids. SiGe island formation and evolution are studied by systematically varying the Ge coverage and pit spacing and quantitative data on the influence of the pattern periodicity on the SiGe island volume are presented. The presence of pits allows the fabrication of uniform island arrays with any of their equilibrium shapes.

X-ray Nanodiffraction on a Single SiGe Quantum Dot inside a Functioning Field-Effect Transistor

For advanced electronic, optoelectronic, or mechanical nanoscale devices a detailed understanding of their structural properties and in particular the strain state within their active region is of utmost importance. We demonstrate that X-ray nanodiffraction represents an excellent tool to investigate the internal structure of such devices in a nondestructive way by using a focused synchotron X-ray beam with a diameter of 400 nm. We show results on the strain fields in and around a single SiGe island, which serves as stressor for the Si-channel in a fully functioning Si–metal–oxide semiconductor field-effect transistor.

Assessment of Electron Mobility in Ultrathin-Body InGaAs-on-Insulator MOSFETs Using Physics-Based Modeling

We have investigated the electron mobility in ultrathin-body InGaAs-on-insulator devices using physics-based modeling that self-consistently accounts for quantum confinement and covers band-structure effects in ultrathin III-V layers. Scattering by nonpolar and polar acoustic and optical phonons, surface roughness, and thickness fluctuations, Coulomb and alloy disorder have been included in the calculations. The modeling, calibrated and verified on experimental data from the literature, has revealed a strong influence of thickness fluctuations caused by the light effective mass of Γ valley electrons. Our results indicate that InGaAs-on-insulator MOSFETs are more influenced by interface properties compared with silicon-on-insulator devices and outperform them only above certain body thickness that depends on interface quality.

n-Channel MOSFETs Fabricated on SiGe Dots for Strain-Enhanced Mobility

The silicon germanium dots grown in the Stranski-Krastanow mode are used to induce biaxial tensile strain in a silicon capping layer. A high Ge content and correspondingly high Si strain levels are reached due to the 3-D growth of the dots. The n-channel MOS devices, referred to in this letter as DotFETs, are processed with the main gate segment above the strained Si layer on a single dot. To prevent the intermixing of the Si/SiGe/Si structure, a novel low-temperature FET structure processed below 400°C has been implemented: The ultrashallow source/drain junctions formed by excimer-laser annealing in the full-melt mode of ion-implanted dopants are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing, and compared to reference devices, an average increase in the drain current of up to 22.5% is obtained.

Silicon-Filled Rectangular Waveguides and Frequency Scanning Antennas for mm-Wave Integrated Systems

We present a technology for the manufacturing of silicon-filled integrated waveguides enabling the realization of low-loss high-performance millimeter-wave passive components and high gain array antennas, thus facilitating the realization of highly integrated millimeter-wave systems. The proposed technology employs deep reactive-ion-etching (DRIE) techniques with aluminum metallization steps to integrate rectangular waveguides with high geometrical accuracy and continuous metallic side walls. Measurement results of integrated rectangular waveguides are reported exhibiting losses of 0.15 dB/ λg at 105 GHz. Moreover, ultra-wideband coplanar to waveguide transitions with 0.6 dB insertion loss at 105 GHz and return loss better than 15 dB from 80 to 110 GHz are described and characterized. The design, integration and measured performance of a frequency scanning slotted-waveguide array antenna is reported, achieving a measured beam steering capability of 82 ° within a band of 23 GHz and a half-power beam-width (HPBW) of 8.5 ° at 96 GHz. Finally, to showcase the capability of this technology to facilitate low-cost mm-wave system level integration, a frequency modulated continuous wave (FMCW) transmit-receive IC for imaging radar applications is flip-chip mounted directly on the integrated array and experimentally characterized.

SOI vs. bulk FinFET: Body doping and corner effects influence on device characteristics

SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator and their electrical characteristics were compared for different body doping and bias conditions. Subthreshold and on-state performance have been examined and higher drain current in case of SOI FinFET has been explained by investigating enhanced conduction in silicon-oxide interface corners.

Technological constrains of bulk FinFET structure in comparison with SOI FinFET

In order to obtain bulk FinFET characteristics that closely match SOI FinFET characteristics, meaning DIBL below 70 mV/V @ ID = 10-6 A and subthreshold swing below 100 mV/dec @ VDS = 1.2 V, source/drain junction depths must be aligned to the bottom of the gate and the fin width of the bulk FinFET must be 20 nm at most assuming the gate length of 50 nm. Bulk FinFET characteristics can be improved by reducing S/D junction depth with respect to the bottom of the gate (e.g. Deltaxj = -10 nm), which can be easily accomplished in fabrication.

Integration of laser-annealed junctions in a low-temperature high-k metal-gate MISFET

Integration and properties of devices processed by excimer laser annealing are presented. The best results are achieved by shallow implantations into a native-oxide-free silicon surface and laser annealing with the remainder of the device protected by an Al reflective layer. Low-temperature MISFETs are fabricated with a metal-gate high-k gate stack of PECVD SiO2 and ALD Al2O3 with an EOT of 9.2 nm and an Al-gate. The source/drain regions are self-aligned to the metal gate, which also serves as a laser masking reflective layer. Ablation of the masking layer is prevented due to the low thermal resistance of the thin underlying gate dielectric. The measured devices exhibit good current drivability, which improves with higher laser energy. The maximum processing temperature of the presented MISFETs is 400°C and can potentially to be reduced down to 300°C.

Features of electron mobility in ultrathin-body InGaAs-on-insulator MOSFETs down to body thickness of 2 nm

Behavior of electron mobility in UTB InGaAs-OI MOSFETs is studied by physics-based modeling. We have shown that UTB InGaAs-OI devices outperform Silicon-OI MOSFETs only for TS > 6.2 nm, due to high SR scattering. Therefore, improvement of interface quality remains crucial to utilize high electron mobility in extremely scaled InGaAs-OI devices.

Optimum body thickness of (111)-oriented ultra-thin body double-gate MOSFETs with respect to quantum-calculated phonon-limited mobility

Ultra-thin body (UTB) double-gate MOSFETs are foreseen as a solution to scaling issues for sub-20 nm CMOS due to excellent immunity to short-channel effects (SCEs). Transport mechanisms in UTB devices have been extensively investigated over the past years [1–3]. Nevertheless, theoretical considerations have been limited only to (100)-oriented UTB single- (SG) or double-gate (DG) devices while the experimental results are available mostly for (100)- and (110)-oriented SG SOI [2,3]. Therefore, an investigation of mobility-behavior in (111)-oriented UTB DG MOSFETs is neccessary, especially due to promising results of UTB FinFETs fabricated on (110) wafers with (111) active sidewalls [4].