Jun Nakai

Semiconductor memory device with sense amplifier power supply configuration capable of supplying stable power supply voltage to sense amplifiers

Semiconductor memory device capable of setting substrate voltage shallow in disturb test mode and self refresh mode

Reference voltage generating circuit of semiconductor memory device

Semiconductor memory device capable of setting the magnitude of substrate voltage in accordance with the mode

Semiconductor memory device with hierarchical control signal lines

Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit

Reference voltage generation circuit for semiconductor memory device

Data output circuit has buffer stage containing pull-up and pull-down transistors, high and low level data output control stages and substrate potential switching stage

Halbleiterspeichereinrichtung die einen Normalbetriebsmodus, einen Störungstestmodus und einen Selbst-Auffrischmodus aufweist A semiconductor memory device having a normal mode of operation, a fault test mode and a self refresh mode,

A semiconductor memory device having a normal mode of operation, a fault test mode and a self refresh mode,