Yasuji Nagayama

A 55ns 64K dynamic MOS RAM with tripple diffused MOS transistor

To obtain the higher performance dynamic MOS RAM, there exist three key parameters for device technologies. The higher performance transistor, the lower resistance interconnections and the smaller stray capacitance realize a high speed and low power operation. The tripple diffused MOS transistor (T.D.T) which satisfies these requirements has been proposed. A novel 64K dynamic MOS RAM with a tripple diffused structure of 2.0\microm gate length has been successfully fabricated. A typical access time of 55nsec was obtained at the power dissipation of 150mW. This excellent electrical characteristics was become possible by the tripple diffused MOS transistor which reduced the short channel effects, the gate to source/drain overlap capacitance and the parasitic resistance.

A 50 ns 4K static DSA MOS RAM

An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.

Diffusion Length Measurement Using Dynamic MOS RAM

A new method for the diffusion length measurement has been proposed using the minority carrier injection in the conventional 64 K dynamic RAM. The temperature dependence of the diffusion length has been measured by this method. The experimental results confirmed the validity of this method for the dynamic RAM analysis.

An effect of the subthreshold current on scaled-down MOS dynamic RAMs

Data-output holding characteristics of MOS dynamic RAMs with 2.5 /spl mu/m design rules are studied by employing the hidden-RAS-only-refresh mode. It is verified that the noise voltage caused by internal circuit operation increases the subthreshold current and that the clamp circuitry effectively decreases the subthreshold current.