Kazuhiro Shimotori

Fully boosted 64K dynamic RAM with automatic and self-refresh

A novel high-speed low-power 64K dynamic RAM with enough margin has been attained using a double polysilicon and 3-/spl mu/m process technologies. To obtain a low soft error rate below 1/spl times/10/SUP -6/ errors per device hour without sacrificing the high-speed and low-power operation, some novel approaches are proposed in the circuit and device designs. In particular, fully boosted circuits and the Hi-C cell structure with polysilicon bit line are designed to increase the margin of the single 5-V power supply 64K dynamic RAM. The fabricated device provides a typical access time of 90 ns and an operating power of 190 mW at 25/spl deg/C. Also, the design features of the automatic and self-refresh functions on the same chip are described.

Fully Ion Implanted DSA MOS IC

Threshold voltage (Vth) controllability of diffusion self-aligned (DSA) MOS FET fabricated by a full ion implantation and N2 drive-in technique has been examined and analyzed. As the p-type diffused region (base) and the n-type diffused region (source) were formed by this method, the impurity profiles of these layers became reproducible and Vth controllability were improved as compared with the usual thermal predeposition process. A simplified Vth model showed a good agreement with the experimental results. The performance of DSA ED MOS IC has been also discussed. In the 19 stage ring oscillators, the propagation delay time per unit gate was 0.36 ns (Vdd=8.0 V) for high speed design and the power-delay product was 0.055 pJ (Vdd=2.7 V) for low power design. A 1024-bits random access memory has been developed on the basis of above mentioned results, and the access time of 50 ns has been obtained.

New Dynamic RAM Cell Combined with Hi–C Structure

A new dynamic RAM cell combined with the Hi–C structure is proposed and its effectiveness is confirmed. The feature of the new cell is to isolate each cell capacitor by the p+-region of the Hi–C structure, instead of the thick SiO2 layer. As the result, the new cell reduces the loss in the storage capacitance by the lateral oxidation, in spite of the conventional LOCOS process. The storage capacitance of the new cell is 13% larger than that of the conventional one. The threshold voltage of the parasitic transistor for isolating adjacent cells was 2.1 V. The breakdown voltage of the new cell was 12 V, which was determined by the p-n junction of the Hi–C structure. The leakage current of the new cell was the same as that of the conventional one.

A 50 ns 4K static DSA MOS RAM

An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.