Takao Nakano

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K /spl times/ 8 full CMOS RAM has been developed with 2-/spl mu/m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six-transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in speed, the second poly-Si layer was replaced with a polycide (poly-Si + MoSi/SUB 2/) layer, thus providing a 50-ns address access time.

A 64Kb full CMOS RAM with divided word line structure

An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed.

Design consideration of a static memory cell

Describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a DC stability factor introduced from transfer curves of the inverters in the cell. The criteria use only static conditions for read/write/retain operations. The designed cell, considering mask-misalignment, measured 22.8/spl times/27.6 /spl mu/m with 2.5 /spl mu/m layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

A 90ns 1Mb DRAM with multi-bit test mode

A 1Mb DRAM using a half Vcc biased memory cell with a reduced electric field of 2MV/cm will be reported. A shared sense amplifier design and a continous nibble mode are also included. Additionally, a test pin allows testing as a 256K×4 memory. Die is 65mm2.

Fully boosted 64K dynamic RAM with automatic and self-refresh

A novel high-speed low-power 64K dynamic RAM with enough margin has been attained using a double polysilicon and 3-/spl mu/m process technologies. To obtain a low soft error rate below 1/spl times/10/SUP -6/ errors per device hour without sacrificing the high-speed and low-power operation, some novel approaches are proposed in the circuit and device designs. In particular, fully boosted circuits and the Hi-C cell structure with polysilicon bit line are designed to increase the margin of the single 5-V power supply 64K dynamic RAM. The fabricated device provides a typical access time of 90 ns and an operating power of 190 mW at 25/spl deg/C. Also, the design features of the automatic and self-refresh functions on the same chip are described.

Soft error improvement of dynamic RAM with Hi-C structure

A novel Hi-C RAM cell is proposed for reducing the alpha-particle-induced soft error rate. The novel cell utilizes the doubly-implanted Hi-C struture combined with the boosted storage gate, which provides much alignment tolerance to the implantation steps for the Hi-C cell. This Hi-C cell having a charge storage capacity 30% larger than that of the conventional cell results in one order of magnitude decrease in soft errors as compared with the conventional one. The concept of this excellent cell is successfully demonstrated by a 64K dynamic RAM fabricated on the basis of a 3 pm design rule. Experimental results on refresh time of the 64K dynamic RAM indicates that the Hi-C cell has been realized without defective effects on the leakage of the stored charge.

SOFT ERROR ANALYSIS OF FULLY STATIC MOS RAM.

The static MOS RAM with the polysilicon resistive load for the cell has been analyzed with respect to alpha-particle induced soft error phenomena. The analytical model of soft error will be presented and the effective critical charge Qcrit will be derived. Fully static 16 K-bit NMOS RAMs were fabricated as test vehicles, which were exposed to Am-241 radiation sources for an accelerated test method. The error rate depends on the cycle time and the cell pull-up resistance in the shorter cycle time operation. But in the longer cycle mode, it is regardless of them. Some techniques for error rate reduction which involve thinning gate oxide thickness, adopting Hi–C structure and cell layout techniques will be introduced and their effects will be discussed.

A reliable 1-Mbit DRAM with a multi-bit-test mode

A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.

A 90ns 4Mb DRAM in a 300 mil DIP

A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.

A 4-Mbit DRAM with folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell

A 5-V 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b dynamic RAM with a static column model and fast page mode has been built in a 0.8-/spl mu/m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10.9 /spl mu/m/SUP 2/ and requires only a 2-/spl mu/m trench to obtain a storage capacitor of 50 fF with 10-nm SiO/SUB 2/ equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C/SUB B/-to-C/SUB S/ capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300-mil dual-in-line package with performances of 90-ns RAS access time and 30-ns column address access time.