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Dive into the research topics where Masayuki Furumiya is active.

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Featured researches published by Masayuki Furumiya.


symposium on vlsi circuits | 2010

A 2.5kV isolation 35kV/us CMR 250Mbps 0.13mA/Mbps digital isolator in standard CMOS with an on-chip small transformer

Shunichi Kaeriyama; Shinichi Uchida; Masayuki Furumiya; Mitsuji Okada; Masayuki Mizuno

An on-chip transformer-based digital isolator for intelligent power management (IPM) systems is proposed. It greatly reduces the number of chips in IPM systems by allowing integration of isolators in a CMOS chip together with MPUs or gate drivers. With a proposed pulse generation / detection scheme that enables a 5V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced to 1/4∼1/8 that of conventional transformers. A test chip achieves a 2.5kV isolation voltage, a 35kV/us CMR, a 1.6mA static current and a 250Mbps data rate, all which are equal to or superior to those of photo couplers or conventional digital isolators. The high-speed low-power capability expands the application potential to include isolated serial links, medical devices, displays, sensors, etc.


radio frequency integrated circuits symposium | 2011

On-chip vertically coiled solenoid inductors and transformers for RF SoC using 90nm CMOS interconnect technology

Hiroaki Namba; Takasuke Hashimoto; Masayuki Furumiya

This paper presents very small on-chip vertically coiled solenoid inductors (V-solenoid) using 90nm CMOS multilevel interconnect technology. In addition, a variety of areas-saving (10um × 20um) transformers without any additional processing steps are demonstrated: a V-solenoid surrounded by another different inside-diameter V-solenoid (dual-tube transformer), a V-solenoid coiled around another one with same dimensions (a double-helix or DNA-like transformer), and face-to-face V-solenoids (face-to-face transformer). Radio-frequency characteristics were evaluated on the basis of 2-port S-parameter measurements. Measured self-resonance frequencies resulted in higher than 40GHz, and coupling coefficients were larger than 0.6.


Japanese Journal of Applied Physics | 2007

Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors

Naoya Inoue; Ippei Kume; Jun Kawahara; Shinobu Saito; Naoya Furutake; Takeshi Toda; Koichiro Matsui; Takayuki Iwaki; Masayuki Furumiya; Toshiki Shinmura; Koichi Ohto; Yoshihiro Hayashi

Highly reliable metal–insulator–metal (MIM) capacitor with ultra-thin SiN dielectrics is developed on the surface-controlled bottom electrode in nanometer-scales. Coverage of the TiN bottom electrode with a Ta thin layer achieves smooth surface. In addition, this electrode structure exhibits excellent etching controllability even for the MIM with the ultra-thin SiN dielectrics. The smooth surface of the Ta/TiN stacked electrode improves the dielectric characteristics such as leakage, breakdown and time-dependent dielectric breakdown (TDDB) reliability in the MIM capacitors, integrated into Cu dual-damascene interconnects (DDIs). As a result, the SiN-MIM with the Ta/TiN bottom electrode achieves high capacitance of 7 fF/µm2 as well as high reliabilities, which are 20% higher breakdown field and 6000 times longer TDDB lifetime than that without Ta-insertion. These values guarantee the high performance operation for more than 10 years under the environment at 85 °C.


asia pacific microwave conference | 2012

Optimization of metal layers and substrate loss for the 3D solenoid structure inductors

Shinichi Uchida; Kenji Hayashi; Hiroaki Namba; Takafumi Kuramoto; Takasuke Hashimoto; Masayuki Furumiya; Yasutaka Nakashiba; Hiroaki Ohkubo

This paper describes the optimization method on choice of the metal layers and the Si substrate structure about the 3-Dimantional(3D) vertical solenoid inductor on the CMOS process. The optimization of metal layers that constituted 3D structure inductors enable inductors, in which the two layers (Al, M6) stacked structure with area ratio of 0.3 and the three layers (Al, M6 and M5~M3) stacked structure with area ratio of 0.17, in comparison with an octagonal planer inductor. In spite of the reduction of area, the peak Q-factor on the inductor is almost equal. As for the constitution under the 3D solenoid inductors, Q-factor of inductor with PGS was lower than that of inductor without PGS, in the case of inductance <;1nH. Furthermore, the self-resonant frequency(fSR) of inductor without PGS was higher than that of inductor with PGS. As a result the inductor without PGS is available in a higher frequency domain than the inductor of PGS type.


international conference on microelectronic test structures | 2011

Matching characteristics of metal resistors

Hiroaki Namba; Takasuke Hashimoto; Kenji Hayashi; Masayuki Furumiya

This paper describes feasibility study on metal wiring resistors. Using 130nm technology node process, matching characteristics of metal wirings are discussed. It is found that precision of tungsten resistor fabricated by damascene process is as high as those of polycrystalline-silicon and polycrystalline-silicon with silicide resistors in the broad temperature. It is likely that tungsten can provide electrical, mechanical robust and highly reliable resistors.


Archive | 2008

Semiconductor device including MIM element and method of manufacturing the same

Masayuki Furumiya; Takeshi Toda


Archive | 2010

Semiconductor device including metal-insulator-metal capacitor arrangement

Masayuki Furumiya; Kuniko Kikuta; Ryota Yamamoto; Makoto Nakayama


Archive | 2010

Semiconductor device including an inductor that is inductively coupled to another inductor

Masayuki Furumiya; Yasutaka Nakashiba


Archive | 2007

Semiconductor integrated circuit device having a decoupling capacitor

Masayuki Furumiya; Hiroaki Ohkubo; Yasutaka Nakashiba


Archive | 2013

Method of manufacturing semiconductor device including capacitor element provided above wiring layer that includes wiring with an upper surface having protruding portion

Masayuki Furumiya; Takeshi Toda

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Jun Kawahara

Tokyo Institute of Technology

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