Yen-Fu Su

Light degradation prediction of high-power light-emitting diode lighting modules

Light-emitting diode (LED), generally used for indicator light, has been developed for the past 50 years. Recently, LED has attracted many industries in the research and design of their products. However, its low electro-optical conversion efficiency causes redundant heat leading to increased junction temperature and decreased LED luminosity. In this research, a detailed finite element method (FEM) model of a LED module with a proper estimated thermal power and boundary conditions is established using an ANSYS® finite element analysis software. Electrical test method (ETM) and thermocouple measurement are utilized to estimate junction temperature and heat sink temperature, as well as to validate the simulation results. Results from simulation agree with experiment results at a 5% deviation. In the life test of high-power LED modules, the six tested devices had different junction temperatures were conducted in this experiment. Luminosity variations are measured by the integral sphere measurement system. Experiment results show different junction temperatures will influence the light degradation mode. Therefore, it is important to predict and control the junction temperature to improve the LED performance. A detailed FEM model of a LED module is established to simulate the junction temperature. Then, the light degradation mode of this LED module is predicted by the simulation result. This method could rapidly predict the light degradation mode of high power LED lighting modules.

Acceleration factor analysis of aging test on gallium nitride (GaN)-based high power light-emitting diode (LED)

Global warming highlights the effect of light-emitting diodes (LEDs), the advantages of which include lo w pollution and power consumption, as well as a long operation lifetime. However, LED research and development is limited by Illuminating Engineering Society of North America (IES) LM-80-08. This standard reliability test, which is utilized by most LED companies, is time-consuming and prolongs time-to-market. LEDs are degraded by various types of stresses, including temperature, current, and optical stresses. Thus, this study proposes an accelerated aging test for high-power LEDs under different high-temperature stresses without input current. 1-W LEDs based on gallium nitride (GaN) from the same series were obtained as test samples. At the beginning of the accelerated aging test, the device structure is presumably known. This test aims to (i) extrapolate the degradation model to accurately estimate lifetime; and (ii) propose a method to shorten IES LM-80-08 and TM-21-11, which last for a minimum of 6000 h. The results of the accelerated aging test show that sufficiently high-temperature stress effectively shortens the unstable period of the LED chip. During aging, light output degraded as well, and the activation energy of the degradation process was 0.65 eV. This value was obtained by applying the Arrhenius model as the prediction model for the lumen maintenance and temperature of the LED. The LED lifetime estimated by the prediction model varied from that projected by the experimental method by only 10%.

Reliability analysis of 3D IC integration packaging under drop test condition

Consumer electronic products are evolving toward smaller size and higher efficiency. 3D IC packaging has smaller form factor and lower signal delay compared with conventional packaging. Thus, it has been widely used in mobile electronic devices. Mobile electronic device is prone to being dropped during operation. Hence, the drop reliability of electronic packaging is an important issue in 3D ICs. Numerous 3D IC packaging issues, such as fabrication process, structure design, and thermal cycling reliability have been studied. However, few studies focus on 3D packaging drop reliability assessment. Conventionally, board level drop test is widely used in determining the drop reliability of electronic packaging. In this study, 3D IC packaging structure is established by using the finite element (FE) analysis software ANSYS/LS-DYNA 3D®. The simulation result is validated by using the board level drop test. The dynamic behavior of 3D IC packaging during board level drop test was observed. Parametric study was also performed to study the effect of structure size and material. Unlike under thermal cycling test condition, increasing chip stacking number may reduce the reliability of copper bumps under drop test condition. Moreover, adding underfill between interposer and test board can enhance solder ball reliability. However, copper bump reliability is reduced, as the interposer under certain thickness.

Thermal analysis and reliability assessment of power module under power cycling test using global- local finite element method

Insulated gate bipolar transistor (IGBT) power modules have acquired fast switching and low conduction loss characteristics. Because of these electrical characteristics, the IGBT has been widely applied in power supplies, e.g. hybrid electric vehicle, wind power generation, etc. However, the IGBT during rapid transient operation under high power can cause the IGBT chip to lead high junction temperature and high temperature gradients. Furthermore, because of the coefficient of thermal expansion (CTE) mismatch between the various material layers, the bonding wires and the solder joints are subjected to thermo-mechanical stress which cause solder fatigue and bonding wire failure, and then affect the reliability of IGBT under actual operation conditions. A 3-D finite element (FE) model was established base on real test samples. The simulation results found that the maximum junction temperature 112.5 °C is observed at the middle of IGBT chip under the load current of 40 A. Then analyze the mechanical behaviors of IGBT, the structural simulation results show that under a cyclic power environment, the stress concentration within the wire, caused by the CTE mismatch between the wire and the IGBT chip. Therefore, the wire/chip interface is the weaker portion of the power module. Finally, according to the life prediction models of literatures, this paper assessed the reliability of bonding wire in order to investigate the effects of thermal stress and strain on reliability during power cycling test.

Development of double-sided with double-chip stacking structure using panel level embedded wafer level packaging

In recent years, consumer electronics demand has been geared towards lightweight, high capacity, and high efficiency small form factor devices. These characteristics can be achieved by using three-dimensional (3D) integrated circuit (IC) technology. This study proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. This structure consists of two or more thin dies, chip carriers, through mold vias (TMV), and interconnection structures. The thermal performance of the proposed packaging structure is examined and discussed by using finite element (FE) analysis. An FE model of the WLP is also established to compare the thermal performance of conventional WLP and the proposed packaging structure. The proposed packaging structure has a larger size and silicon carrier, which reduces its thermal resistance from 49 °C/W to 39 °C/W. By adopting the proposed design guidelines, including carrier material selection, and designating thermal vias and chip/package size ratios, FE analysis determined that the thermal performance of the proposed packaging structure can be further improved, thereby enhancing its suitability for applications with high power density.

Determination of silicon die initial crack using acoustic emission technique

Three-dimensional chip stacking packaging has become increasingly popular in the electronic packaging industry because of the present market demand on high performance, high capacity and small form factor products. As a result, silicon wafers have to be ground through wafer-thinning processes to achieve greater packaging density. However, induction of cracks on the chips during stacking process or with the use of a device is possible. Therefore, the current research aims to determine the maximum allowable force on a (1 0 0) silicon die using ball-breaker test with an acoustic emission (AE) system. To compare with the experiment data, the finite element analysis was employed using commercial software ANSYS/LS-DYNA3D® to determine the silicon die strength. The results show that the maximum allowable force for a 30 mm × 30 mm × 0.2 mm (1 0 0) silicon is 14.42 N. The value was introduced to simulation to determine the strength of silicon die. The strength of silicon die is 618 MPa, which is lower than that obtained from a previous research that conducted the ball-breaker test without an AE system, the allowable strength is defined as when silicon is fully cracked. The advantage of the method developed in this research is the AE system could detect the failure instantly and obtain the event of initial cracking. The modified ball-breaker test could avoid an overestimation in determining the die strength.

Stress/stain assessment and reliability prediction of through silicon via and trace line structures of 3D packaging

This study assesses the reliability life of 3D chip stacking packaging developed by the Industrial Technology Research Institute (ITRI). The simulation results show that the trends of stress of through silicon via (TSV) structures with different chip stacking numbers are nearly constant during thermal stress analysis. Therefore, the simplified two-layer chip stacking model is adopted to analyze the thermal-mechanical behavior of TSV. Subsequent thermal cycle simulations show that the maximum equivalent plastic strain occurs at the bottom trace near the substrate. The Engelmaier model is selected to predict the fatigue life of TSV, and it shows that the simulation results match experimental results. The effects of the substrate material and underfill are also discussed. TSV structures with BT substrates, which can replace silicon substrates, could effectively protect bottom traces and prevent fractures occurring from copper trace. In addition, when a TSV structure with an underfill is subjected to thermal cycle conditions, chips and vias experience more stress, but copper traces are protected by the underfill. No apparent alteration in reliability performance is detected.

A method to compensate packaging effects on three-axis MEMS accelerometer

This paper discusses about the residual stress and packaging effect of three-axis micro-electro-mechanical system (MEMS) accelerometer. The 3D FEM model with modal analysis method is adopted for the resonance frequency estimation. This paper also presents a simple compensation model for trimming the offset of capacitance differentiation using the measured resonance frequency. This trimmming methodology can be realized by adjusting circuit gain in real product.

Determination of the junction temperature of Gallium Nitride (GaN)-based high power LED under thermal with current loading conditions

This In recent years, high brightness with low power consumption green power device, Light emitting diodes (LEDs), has become more and more popular. In this highly competitive area, how to effectively let the LED product meet the spec requirements and shorten the design cycle becomes more and more important. Currently, the common reliability test of LED is according to IES LM80-08, which is time consuming and will prolong the time-to-market schedule. In our previous researches, a modified accelerated aging test algorithm which can shorten the testing time on high power LEDs using different high temperature stress without input current was successfully proposed. The effect of input current with temperature loading may have to consider in accelerated aging test. For the accelerated aging test with the loading conditions of temperature and current, this research proposed a methodology to simulate the junction temperature of the LED using finite element (FE) method with thermal theories. The junction temperature of LED chip can be obtained by JEDEC standard EIA/JESSD51-1, which is based on the forward voltage method, and the simulation result was validated with the experiment result. In summary, the predicted temperature would help the accelerated aging test essentially. It significantly reduced the try-and-error time in experiment. The model can simulate the junction temperature under working current in different ambient temperature. Based on this methodology, the simulation result would apply to the accelerated aging test with developed degradation prediction model in the future.

Determination of Initial Crack Strength of Silicon DieUsing Acoustic Emission Technique

The current market demand for high-efficiency, high-performance, small-sized electronic products has focused attention on the use of three-dimensional (3D) integrated circuits (IC) in the design of electronic packaging. Silicon wafers can be ground and polished to reduce their thickness and increase the chip stacking density. However, microcracks can result from the thinning and stacking process or during use of an electronic device over time; therefore, estimation of the cracking strength is an important issue in 3D IC packaging. This research combined the ball breaker test (BBT) with an acoustic emission (AE) system to measure the allowable force on a silicon die. To estimate the initial crack strength of a silicon die, the BBT was combined with finite-element (FE) analysis. The AE system can detect the initial crack and the subsequent bulk failure of the silicon die individually, thus avoiding overestimation of the die strength. In addition, the results of the modified ball breaker test showed that edge chipping did not affect the silicon die strength. However, the failure force and silicon die strength were reduced as the surface roughness of the test specimen increased. Thus, surface roughness must be controlled in the BBT to prevent underestimation of the silicon die strength.