Tuan-Yu Hung

Thermal–mechanical behavior of the bonding wire for a power module subjected to the power cycling test

Abstract Two analytical methods were proposed in this research, coupled electro-thermal finite element (FE) analysis and thermal–mechanical FE analysis, to analyze the mechanical behavior of bonding wire of power module under cyclic power loads, and the International Electrotechnical Commission standard is adopted in conducting a power cycling test. The exterior temperature distribution was measured by an infrared thermometer. Moreover, the junction temperature is calculated from the given thermal impedance of the semiconductor chip, chip power loss, and case temperature. Subsequently, the simulated temperature distribution via electro-thermal FE analysis is compared with experimental results to validate the methodology used in the aforementioned analysis. The analysis shows compressive stress at the wire/chip interface due to CTE mismatch between the aluminum and the chip. Moreover, the major driving force contributing to the shear stress at the interface is the self-expansion of the wire bump.

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

Accompanying the popularization of portable and handheld products, high reliability under board level drop test is a great concern to semiconductor manufacturers. In this study, a stress-buffer-enhanced package with fan-out capability is proposed to meet the high requirement of drop test performance. Both drop test experiment and numerical simulation were performed. The results showed the first failure of proposed package passed over 100 drops (mean-life-to-failure over 240 drops). Moreover, the failure of broken trace metal in the stress-buffer-enhanced package which is different from the solder joint failure in the conventional wafer level package was observed both in experiments and dynamic simulations. Simulation results were validated with experimental data and explained how the proposed stress-buffer-enhanced package improved drop test performance.

Life Prediction of High-Cycle Fatigue in Aluminum Bonding Wires Under Power Cycling Test

In this paper, a 3-D finite-element (FE) model was established based on real test samples. Coupled electrothermal and thermal-mechanical FE analyses were conducted to analyze the mechanical behavior of bonding wire under cyclic power loading. The current crowding phenomenon may be improved by increasing the wire number. The junction temperature can be decreased by decreasing the joule heat from the current crowding around the bonding wire. The findings suggest that the power module with wire configuration design shall be operated in a higher power load; meanwhile, the identical reliability can be guaranteed. The temperature predicted by the simulation was consistent with the experimental data. Incremental equivalent plastic strain was not observed when the current loading was low. However, the plastic ratio progressively enhanced with the current load. With a high current load, the yielding effect should be considered. Plastic strain dominated the failure mechanism. The concepts of high- and low-cycle fatigue should be incorporated into the life prediction model for modules subjected to low and high current loadings, respectively. After the simulation results were validated with the experimental data, two models for the design of power modules were proposed.

Investigation of stress-buffer-enhanced package subjected to board-level drop test

In this research, the objective is to develop a stress-buffer-enhanced package subjected to board level drop test under a high-G impact drop; both drop test experiments and ANSYS/LS-DYNA simulations are executed. Many researchers indicate that solder joints in wafer level chip scale package (WLCSP) are the weakest portion in board-level drop test because of the large relative motion between the board and the chip mounted on it and the brittle intermetallic compound (IMC) layer. To compare with the failure mechanism of traditional WLCSP structure, the stress-buffer-enhanced package shifts its failure mode to the trace damage on the chip side. Because the soft stress buffer layer has relatively larger elongation to reduce the impact to the solder joints, the corner between the solder joints and connection trace becomes the critical region which may break due to the stress concentration effect. In the drop test experiment, the proposed stress-buffer-enhanced package passed over 100 drops (most packages passed 240 drops); the performance far exceeds the JEDEC criterion which is 30 drops. Following, three phases of drop test simulation are conducted to elucidate the mechanical behavior of board and packages during the blink of impact. Results show that the stress at proposed stress-buffer-enhanced package is much smaller than that at conventional WLCSP. On the other hand, the trace stress level of proposed stress-buffer-enhanced package is slightly larger than that of conventional WLCSP. Simulation results explain the impact loading absorption of thick dielectric layer to reduce the stress level of solder joints.

Thermal design and transient analysis of insulated gate bipolar transistors of power module

Insulated gate bipolar transistors (IGBT) have been utilized in high power and fast switching applications for power management. Research on transient thermal performance assessment has become imperative because of the excessive heat generated from the IGBT chip. In this study, the transient thermal performance of the power chip under the power cycling test was investigated, and the temperature history on the chip was recorded by an infrared thermometer during the test. The test conditions of the experiment were based on: the International Electrotechnical Commission (IEC) standard. The current density distribution of the IGBT chip was investigated by electro-thermal finite element (FE) analysis. In order to validate the methodology for FE analysis, the predicted temperature distribution was compared with the experimental data under the same electrical load. Furthermore, the temperature-dependent material property was employed in electro-thermal FE analysis. The results show that the current crowding effect occurred near the periphery of the bonding wires. Moreover, the solder under the chip provided a significant route of heat dissipation in the power chip, when high power was applied.

Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test

Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.

Reliability analysis of 3D IC integration packaging under drop test condition

Consumer electronic products are evolving toward smaller size and higher efficiency. 3D IC packaging has smaller form factor and lower signal delay compared with conventional packaging. Thus, it has been widely used in mobile electronic devices. Mobile electronic device is prone to being dropped during operation. Hence, the drop reliability of electronic packaging is an important issue in 3D ICs. Numerous 3D IC packaging issues, such as fabrication process, structure design, and thermal cycling reliability have been studied. However, few studies focus on 3D packaging drop reliability assessment. Conventionally, board level drop test is widely used in determining the drop reliability of electronic packaging. In this study, 3D IC packaging structure is established by using the finite element (FE) analysis software ANSYS/LS-DYNA 3D®. The simulation result is validated by using the board level drop test. The dynamic behavior of 3D IC packaging during board level drop test was observed. Parametric study was also performed to study the effect of structure size and material. Unlike under thermal cycling test condition, increasing chip stacking number may reduce the reliability of copper bumps under drop test condition. Moreover, adding underfill between interposer and test board can enhance solder ball reliability. However, copper bump reliability is reduced, as the interposer under certain thickness.

Uncertainty and reliability analysis of chip scale package subjected to Board-level Drop test

The Board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw, which is not considered in JEDEC. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. Accordingly, the drop induced stress in solder joints may be influenced by the tightness of the screw The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of strain, and the vibration frequency is smaller than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude.

Analysis of LED wire bonding process using arbitrary Lagrangian-Eulerian and explicit time integration methods

Wire bonding is one of the main processes used to connect the signal of light emitting diode (LED) chips. Failures, such as pad peeling, cracking, and delamination, affect the development of LED, and some of these failures are influenced by the wire bonding process. This research aims to construct an effective simulation methodology for the impact stage of the wire bonding process. An effective simulation methodology utilizing the explicit method with a second level accuracy arbitrary Lagrangian-Eulerian (ALE) algorithm is successfully achieved. Only a 0.5% discrepancy in ball height between this model and the actual wire bonding sample is observed after the impact stage, and the geometry of the bonded wire is similar to that of the actual wire. The finite element (FE) model established in this research not only conquers the element distortion problem, but proposes an effective methodology for simulating the wire bonding process in the future.

Investigating the temperature effect of reliability on integration IC 3D packaging under drop test

Technological developments and increasing user demand have driven the evolution of electronic packaging from traditional single-chip packaging to multi-chip packaging, i.e., three-dimensional integrated circuit (3D-IC) packaging. The main advantages of 3D-IC packaging are its small size and lower signal delay. Thus, 3D-IC packaging has been broadly used in mobile electronic devices. Mobile electronic devices are prone to being dropped because of their portability. During drop impact, the temperature inside the packages becomes higher than ambient temperature especially for 3-D packaging, which would influence physical behavior of packaging. A simulation that uses the Input-G method was adopted to analyze the dynamic behavior of electronic packaging. Finite element (FE) model analysis that considers glass transition temperature (Tg) was performed to investigate the effect of temperature. The results showed that the reliability of electronic packaging with underfill might be worse than that without underfill when temperature loading is higher than Tg. This study focuses on drop reliability and considers the effect of Tg. An FE model was established based on a real 3D-IC integration package to predict the drop life by using CoffinManson semi-empirical equation. First, thermal stress analysis would be The drop analysis conducted after the thermal stress analysis indicates that the plastic strain of solder joint increased evidently when considering the effect of temperature during drop analysis and that a temperature higher than Tg has a more obvious influence on strain accumulation during thermal stress analysis than during drop impact analysis. Finally, the drop reliability of 3D-IC was predicted. For a structure without underfill, the drop life can be predicted reasonably, whereas it will be overestimated when the structure has underfill. These different findings may be due to the perfect bonding provided by the underfill during each drop in the simulation, which is unlike actual, real-world situations.