Shin-Yueh Yang

Analysis of Thermal and Luminous Performance of MR-16 LED Lighting Module

Light emitting diode (LED) with a long lifetime, low power consumption, and low pollution has been successfully applied in many products. However, due to its low electro-optical conversion efficiency, high percentage of input power transformed to redundant heat, thus increasing the LED temperature. This phenomenon decreases the luminous flux, changing light color, and useful life span of LED. Therefore, thermal management becomes an important issue in high power LED. In this paper, the variation of luminous flux and light color for different LED lighting modules under long time operation has been measured and discussed. In addition, a detailed finite element model of LED lighting module, MR-16, with a corresponding input power and suitable boundary conditions is established by using the ANSYS finite element analysis program. Furthermore, to validate the simulation results, the current-voltage-temperature method for characterization of a diode is utilized to measure the junction temperature of LED chip indirectly and compare with simulation results. After the simulation is validated, various thermal performance assessments under the different design parameters of the LED package and lighting module are also investigated in this paper. The methodology and analysis results of this paper can provide a guideline for the LED lighting module such as MR-16 design in the future.

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

Accompanying the popularization of portable and handheld products, high reliability under board level drop test is a great concern to semiconductor manufacturers. In this study, a stress-buffer-enhanced package with fan-out capability is proposed to meet the high requirement of drop test performance. Both drop test experiment and numerical simulation were performed. The results showed the first failure of proposed package passed over 100 drops (mean-life-to-failure over 240 drops). Moreover, the failure of broken trace metal in the stress-buffer-enhanced package which is different from the solder joint failure in the conventional wafer level package was observed both in experiments and dynamic simulations. Simulation results were validated with experimental data and explained how the proposed stress-buffer-enhanced package improved drop test performance.

Light degradation prediction of high-power light-emitting diode lighting modules

Light-emitting diode (LED), generally used for indicator light, has been developed for the past 50 years. Recently, LED has attracted many industries in the research and design of their products. However, its low electro-optical conversion efficiency causes redundant heat leading to increased junction temperature and decreased LED luminosity. In this research, a detailed finite element method (FEM) model of a LED module with a proper estimated thermal power and boundary conditions is established using an ANSYS® finite element analysis software. Electrical test method (ETM) and thermocouple measurement are utilized to estimate junction temperature and heat sink temperature, as well as to validate the simulation results. Results from simulation agree with experiment results at a 5% deviation. In the life test of high-power LED modules, the six tested devices had different junction temperatures were conducted in this experiment. Luminosity variations are measured by the integral sphere measurement system. Experiment results show different junction temperatures will influence the light degradation mode. Therefore, it is important to predict and control the junction temperature to improve the LED performance. A detailed FEM model of a LED module is established to simulate the junction temperature. Then, the light degradation mode of this LED module is predicted by the simulation result. This method could rapidly predict the light degradation mode of high power LED lighting modules.

Fabrication process simulation and reliability improvement of high-brightness LEDs

Abstract To enhance the light extraction efficiency and thermal performance of AlGaInP light-emitting diodes (LEDs), the wafer bonding technique which can replace the GaAs substrate with other high thermal conductivity substrates was applied. However, this technique may make the film crack during either the removal etching process of the GaAs substrate or the annealing process after the GaAs removal. Therefore, this crack problem is an important issue in the reliability/yield of high-brightness LEDs. In this research, a detailed finite element model of the high-brightness AlGaInP LED, which is replaced by the GaAs substrate with high thermal conductivity substrate through the Au–In metal bonding technique, was developed and fabricated. In addition, the mechanical behavior of wafer-level metal bonding was also simulated by finite element analysis (FEA) and validated by experimental measurements. Hence, the above validated simulation technique combined with process modeling is used to understand the stress variation of the multilayer structure of AlGaInP LED during the fabrication process and to find the principal cause of the film crack.

Determination and Verification of Silicon Die Strength Using Ball-Breaker Test

3D or stacked-die packages are becoming increasingly popular in the electronic packaging industry because of the current market demand for cheaper and smaller products with high performance characteristics. As a result, the IC silicon wafers have to be grinded through wafer-thinning processes to achieve greater packaging density. However, it is possible to induce crack of the chips during stacking process or in the use of the device. Therefore, this study aims to determine the die strength of (1 0 0) silicon which can provide to designers for reliability of the die. Several methods have already been adopted to determine the strength of silicon die. These methods include three-point bending test (3PB), four-point bending test (4PB) and ball-breaker test. However, 3PB and 4PB have difficulty for application not only in experiment set ups and silicon die sample preparation aspects but also in actual use because of their sensitivity to both edge and surface defects. Therefore, the ball-breaker test is then proposed in this study to measure the maximum allowable force of silicon die. Meanwhile, comparing with experiment data, the finite element method (FEM) analysis using commercial software ANSYS/LSDYNA3D® are introduced to determine the silicon die strength. Moreover, the 3D model of the ball-breaker test is verified through the Hertzian contact theory. The effect of the thickness on silicon die strength and the failure modes are also discussed in this study. As the applied force increases, the crack appears on the edge of the contact area on the top surface and flare out within the die. However, the radial crack occurs on the bottom surface while the bending effect on the bottom side of the test die has become significant as the die thickness decreases. The early failure may occur at the position and then crack through the top surface causing the die breakage. In other words, the determined strength in this experiment decreases as the thickness of test die becomes increasingly thin. Furthermore, the simulation results show that the allowable force of silicon dies increases as the softer foundation material is applied while the bending behavior is not significant. However, the breakage of the thinner test die placed on the softer material is much easier to happen because the tensile stress on the bottom surface resulting from the bending behavior increases rapidly and significantly influences the die breakage.Copyright

Determination of maximum strength and optimization of LED chip structure

High-power light emitting diodes (LEDs) are found in a number of applications in high-volume consumer markets, such as illumination, signalling, screen backlights, automotives, and others, because of the numerous advantages of LEDs, including low power cost, long life span, and high efficiency. During the manufacturing process, the high-power LED chips are subjected to mechanical and thermal loadings. Wire bonding is one of the major processes in the LED packaging process that provide electrical interconnection between the bonding pad and the lead. However, due to bad parameter setup in a wire bonder, the LED will crack and the pad will peel after wire bonding. In this study, the strength of LED is determined for the design requirement in order to ensure good reliability of wire bonding. Pointload test (PLT) and focused ion beam (FIB) are used to determine the maximum allowable force the epilayer can withstand, which is approximately 75 g. By combining the finite element method and experimental data, a useful design tool to confirm LED die strength is provided. Finite element results of contact analysis show that the stress concentration area is located on the edge of the pin and maximum stress (227 MPa) occurs in the epilayer. Parametric study is employed to find ways to reduce stress in LED layer. The results indicate that increasing pad thickness is the major factor that can reduce stress and enhance LED die strength. PLT and FIB experiments are also performed to confirm simulation results.

Determination of silicon die initial crack using acoustic emission technique

Three-dimensional chip stacking packaging has become increasingly popular in the electronic packaging industry because of the present market demand on high performance, high capacity and small form factor products. As a result, silicon wafers have to be ground through wafer-thinning processes to achieve greater packaging density. However, induction of cracks on the chips during stacking process or with the use of a device is possible. Therefore, the current research aims to determine the maximum allowable force on a (1 0 0) silicon die using ball-breaker test with an acoustic emission (AE) system. To compare with the experiment data, the finite element analysis was employed using commercial software ANSYS/LS-DYNA3D® to determine the silicon die strength. The results show that the maximum allowable force for a 30 mm × 30 mm × 0.2 mm (1 0 0) silicon is 14.42 N. The value was introduced to simulation to determine the strength of silicon die. The strength of silicon die is 618 MPa, which is lower than that obtained from a previous research that conducted the ball-breaker test without an AE system, the allowable strength is defined as when silicon is fully cracked. The advantage of the method developed in this research is the AE system could detect the failure instantly and obtain the event of initial cracking. The modified ball-breaker test could avoid an overestimation in determining the die strength.

Uncertainty and reliability analysis of chip scale package subjected to Board-level Drop test

The Board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw, which is not considered in JEDEC. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. Accordingly, the drop induced stress in solder joints may be influenced by the tightness of the screw The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of strain, and the vibration frequency is smaller than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude.

Determination of Initial Crack Strength of Silicon DieUsing Acoustic Emission Technique

The current market demand for high-efficiency, high-performance, small-sized electronic products has focused attention on the use of three-dimensional (3D) integrated circuits (IC) in the design of electronic packaging. Silicon wafers can be ground and polished to reduce their thickness and increase the chip stacking density. However, microcracks can result from the thinning and stacking process or during use of an electronic device over time; therefore, estimation of the cracking strength is an important issue in 3D IC packaging. This research combined the ball breaker test (BBT) with an acoustic emission (AE) system to measure the allowable force on a silicon die. To estimate the initial crack strength of a silicon die, the BBT was combined with finite-element (FE) analysis. The AE system can detect the initial crack and the subsequent bulk failure of the silicon die individually, thus avoiding overestimation of the die strength. In addition, the results of the modified ball breaker test showed that edge chipping did not affect the silicon die strength. However, the failure force and silicon die strength were reduced as the surface roughness of the test specimen increased. Thus, surface roughness must be controlled in the BBT to prevent underestimation of the silicon die strength.

Evaluation of Die Strength by Using Finite Element Method With Experiment Validation

3-D chip stacking packaging is becoming increasingly popular in the electronics packaging industry because the demand of current market has focused on cheaper products with higher performance characteristics and smaller form factors. Silicon wafers must be ground using wafer-thinning processes to achieve smaller packaging sizes. However, cracks may form in the silicon chips during stacking or while the device is in use. In this paper, the ball-breaker test is used to determine the maximum allowable force on a (1 0 0) silicon die. Finite element (FE) analysis using the commercial software ANSYS/LS-DYNA3-D is introduced to calculate the strength of the silicon die and compared with the experimental findings shows that the results are consistent with Hertzian contact theory. The effects of silicon die thickness and foundation material on the silicon die strength are also discussed in this paper. As the applied force increases, a crack appears on the edge of the contact area and propagates within the die. A decrease in die thickness results in the formation of radial cracks on the bottom surface as well as significant bending effects on the test die. The initial failure may originate from the radial crack and propagate toward the top surface of the die leading to die breakage. The strengths determined in this experiment decrease as the test die becomes thinner. Furthermore, if the insignificant bending behavior is observed, simulation results show that the maximum allowable force on a silicon die increases when a softer foundation material is used. However, a thin test die placed on a soft material is considerably easy to break because the tensile stress on the bottom surface of the die caused by the rapid increase in bending behavior significantly affects die breakage.