Leong Ching Wai

Electromigration study of 50 µm pitch micro solder bumps using four-point Kelvin structure

Electromigration (EM) of micro bumps of 50 µm pitch was studied using four-point Kelvin structure. Two kinds of bumps, i. e., SnAg solder bump and Cu post with SnAg solder were tested. These bumps with thick Cu under bump metallization (UBM) were bonded with electroless Ni/Au (ENIG) pads. The results showed different EM features comparing with larger flip chip joints. Under various test temperatures from 100 to 140 °C, the increasing of electrical resistance under current stressing was mainly due to the formation of the high temperature intermetallic compounds (IMCs). The resistance increase-rate in solder bump interconnects was faster than that of Cu post with SnAg bump joints since there was more low temperature solder and under current stressing, more IMCs would be formed. When Cu post with SnAg bumps were tested at 140 °C with the current density of 4.08×104 A/cm2, after certain stressing time the resistances would reach a plateau region, where the diffusion between different materials, i. e., Cu, Ni and Sn reached equilibrium, and IMCs became stable. Large number of Kirkendall voids and a number of cracks were found in the Cu post interconnects which was caused by the electron wind since less voids and cracks were found in the adjacent bump interconnects. When Cu post with SnAg bumps were tested at 140 °C with the current density of 2.04×104 A/cm2 for 1000 h, the resistance did not reach steady state. The electron flow direction also has an effect on the diffusion of materials. The degradation of resistance increased faster when electrons flow from Cu UBM to ENIG.

Numerical modeling of through silicon via (TSV) stacked module with micro bump interconnect for biomedical device

A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-dimensional plane strain analysis using the global-local technique, based on St. Venants principle, is performed on the diagonal cross-section of the wafer. The thermal-mechanical modeling has shown that the shear stress Sxy at the micro-bump, compressive stress Sy at the interconnection and shear stress Sxy at the TSV are reduced for off-pad via as compared to on-pad via. This is because the CTE mismatch between the micro-bump and TSV is no longer effective when the TSV is offset. Also the work presented that the offset distance of the off-pad via does not have an impact to the compressive stress Sy and shear stress Sxy at the interconnection. There are also no significant changes in the shear stress Sxy at the TSV as the off-pad via moves outward to the die edge. As we knows that the bending stress Sx is a major factor contributing to die cracking due to coefficient of thermal expansion (CTE) mismatch. Our simulation results showed that the bending stress Sx of the top die and bottom die was not affected by increasing the offset distance of the off-pad via even to the die edge. Thus it is an advantage to plate the through-silicon-via away from the micro-bump to avoid stresses complication arises from CTE mismatch.

Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer

This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100μm bump pitch and 1,124 I/O; the other micro-bumped chip had 50μm bump pitch and 13,413 I/O. The TSV interposer size is 25 × 25 × 0.3mm3 with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 × 45mm2 with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 × 10mm2 micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.

Study on silver sintered die attach material with different metal surfaces for high temperature and high pressure (300°c/30kpsi) applications

In this study, Silver sintering material is being evaluated on different metal surfaces for high temperature storage and high temperature plus high pressure test up to 300°C/30kpsi. Three different type of Alumina based ceramic substrates (gold, silver and copper metal finishes) are used as test vehicle in this evaluation. Die attach material and process quality has been evaluated in terms of die shear strength before and after high temperature storage for gold and silver surfaces, further study is the evaluation for the combined test with high temperature and high pressure (HTHP) for plasma treated metal surfaces (silver, gold and copper) and failure mode analysis. Silver-filled epoxy and high temperature epoxy materials are also used as references to make comparison with sintered materials at high temperature storage. After high temperature (300°C) storage test for 500 hours, shear strength of silver surface samples is increased from average shear strength of 17.96N/mm2 to 25.97N/mm2. However, shear strength of gold surface finished (ENEPIG) samples are decreased drastically from average shear strength of 14.78N/mm2 to 0.30N/mm2. A porous layer is observed at the interfaces near the dense Au/Ag alloy between Ni/Pd/Au finished surface and Ag sintering layer where the interfacial failure mode is happened. High temperature (300°C) and high pressure (30kpsi) storage test samples for 500 hours shows relatively higher shear strength for both silver surface and ENEPIG surface while degradation happened on the bare copper surface. After combined HPHT test (300°C/30kpsi/500hours), gold layer in ENEPIG surface is diffused into palladium and nickel layers without creating a porous layer near the Au/Ag alloy and the exhibits good shear strength results which is significantly different behavior from the high temperature storage without pressure. SEM and EDX are used to analyze the cross-sectioned layers after HPHT aging tests. Silver sintering on copper surface shows the lowest shear strength among Ag, Au and Cu substrates. Au substrates has an average shear strength of >20N/mm2, which is higher than Ag substrate which has an average shear strength of >10.9N/mm2.

Process characterization of highly conductive silver paste die attach materials for thin die on QFN

In this paper, die attach process characterization on two type of highly conductive silver paste die attach materials was discussed. The first silver paste die attach materials (DA1) was used as a reference which is silver-loaded epoxy adhesive with high thermal conductivity of 60W/mK and electrical conductivity of 16Ms/m. Second silver paste die attach material (DA2) can be sintered with low pressure or pressure-less at temperature of 220°C to 280°C. DA2 material acquires high thermal conductivity range of 100–170W/mK and electrical conductivity range of 12–15Ms/m. Process specifications were set at die tilt < 1%, average bond line thickness between 25μm to 50μm and full die attach materials coverage without overflow of materials on top of dies surface. Process was optimized with 70μm thin silicon daisy chain chip with die size of 5mm×5mm on Ag plated QFN lead frame for both silver paste materials and achieved the required process specifications. Process optimized on DA1 achieved average bond line thickness ranged from 24.5μm to 30.5μm with die tilt less than 0.24% and DA2 had average bond line thickness ranged from 32.6μm to 44.2 μm with die tilt less than 0.15%. There was further evaluation on die attach process with silver sintered paste for different die thickness (which 50μm, 70μm and 175μm were used) on a fixed die size of 5mm×5mm. Porosity after die attach cure is always a curial factor which affects the modulus and conductivity of the device. Investigation on porosity of cured die attached materials was carrying out on different die size range from 0.5mm × 0.5mm to 5mm × 5mm. This helped to understand the effect of die size on sintering process. Optimization of dispensing pattern and die attach process challenges of thin die attachment were discussed in details in this paper.

Fine pitch copper wire bonding on 45nm tech Cu/low-k chip with different bond pad metallurgy

Wire bonding technology has been widely used in the semiconductor industry for interconnection between device and substrate. Gold wire has been used in industry for many years; however with the increase in the price of gold in the past few years, copper wire has become an alternative. Copper wires have better electrical and thermal performance than gold wire. However due to coppers hardness, the bonding of copper wire to the soft Al bond pad becomes a challenge especially for devices with sensitive and fragile structures underneath the Al bond pad. An optimized Al remnant is required for achieving good reliability [1–2]. A robust bond pad structure with different bond pad material could reduce the impact to structures under the bond pad, minimize Al splash and remove the concern associated with Al remnant for reliability. In this study, copper wire bonding on bond pads with different hardness will be evaluated; they are Al pad and NiPd on top of Al pad. An ASM Eagle Xtreme bonder was used for the study. The forming gas (95%N25%H2) flow rate of 0.4/0.8ℓ per minutes was controlled by a digital flow meter which provides a consistent supply of forming gas. Forming gas maintain an inert environment during the electrode flame-off for free air ball. Capillary with a hole size of 21.6µm, chamfer diameter of 28µm and face angle of 11° was designed for fine pitch bonding with matte surface to enhance the gripping of ball and wire during bonding. A 4N copper with 0.7mil in diameter was used to evaluate the bonding on a Cu/low-k chip with two different bond pad metals with thicknesses of 2.1µm for the Al bond pad and 1.4µm Al/2.5µmNi/0.3µmPd bond pad finish. The NiPd layer used in this study was actually two separate layers which consist of 2.5µm of Ni and 0.3µmPd. Optimized bonding parameters were used on different surfaces to compare the results of bond quality. Comparisons of the deformation of the Al layer and NiPd layer as a result of the bonding was studied. NiPd is harder and could act as a barrier to prevent the direct interaction of the copper wire on the Al bond pad and thus prevent the problems of Al splash especially in fine pitch wire bonding. In this study, target ball size of 34µm were bonded to 55µm bond pad pitch Cu/low-k chips. The effects of the NiPd layer on various parameters were compared with Al bond pad. Evaluated sample were subjected to thermal aging to further understand the effects of temperature on bond quality.

Evaluation of laser solder ball jetting for solder ball attachment process

Due to the perpetual push in microelectronic industry for miniaturization and better performance, the density of input/output counts on the electronic packages is multiplying within a given area. Conventional flux-based solder ball attachment process is fast reaching its bottleneck in satisfying the more restrictive pitch tolerances, and assembling challenges in optoelectronics and micro-electromechanical systems (MEMS) packages. To meet the new packaging requirements, a new flux-less laser solder ball jetting technology has been developed. Despite the various advantages which laser solder ball jetting can offer, it has not been extensively reported. In this paper, fine pitch laser solder ball jetting at 200μm pitch was demonstrated using 120μm SAC305 solder spheres. The reliability of the laser jetted bumps was evaluated and compared against the flux-based reflowed bumps, by subjecting the bumps under high temperature storage (1250C for 24hrs, 500hrs and 1000 hrs) and multiple reflow (5 and 10 times). The quality and reliability of the solder joints were quantified through the solder ball shear test, cross-sectioning, energy dispersive x-ray (EDX) spectroscopy analysis and scanning electron microscopy (SEM) imaging. From our results, laser jetted bumps showed high initial average shear strength of 10.70g/mil2, which eventually decreased to 6.96g/mil2 after 24 hours. Comparing the laser jetted bumps against the flux-based reflowed bumps after 1000 hours of thermal aging and 10 times of reflow, the average shear strength values were persistently higher and the measurements of the IMC thickness were constantly lower. Hence, laser solder ball jetting has proven to be an attractive and alternative solder ball attachment method for strong and reliable solder interconnections.

A Systematic Underfill Selection Methodology for Fine Pitch Cu/Low-k FCBGA Package

In this paper, a systematic underfill selection approach has been presented to characterize and identify favorable underfill encapsulants for 21 times 21 mm2 flip chip ball grid array (FCBGA) package with 150 mum interconnect pitch. A total of six evaluation factors of equal ranking weightage were considered in this underfill selection approach. Based on the approach adopted, we have selected the best underfill material suitable for 15 times 15 mm2 FCBGA packages. The target property ranges for underfill materials proposed by the IBM are further being refined. Now, a wider choice of underfill material was found to be applicable for 15 times 15 mm2 FCBGA packages. The new approach has helped to widen the selection criteria for underfill material used in 15 times 15 mm2 FCBGA packages. These findings will assist researchers in having a wider option in underfill selection for future FCBGA packages, which are more challenging.

Optimization of a microfluidic cartridge for Lab-on-a-chip (LOC) application and bio-testing for DNA/RNA extraction

A bio-microfluidic cartridge has been developed with integrated reservoir and valves for Lab on a chip (LOC) applications, e.g. extracting DNA (Deoxyribonucleic Acid) from human blood. A combination of different materials such as thermoplastic and elastomer are used to fabricate the microfluidic cartridge. A conical shape reservoir with thin membrane sealing is designed to have minimum dead volume in the reservoir after dispensing completely into the chip. An external actuation is used to apply pressure on the thin rubber membrane to push the fluid from the reservoir to the chip and to output collector. The external actuation pushes the fluid through the pin valve and the fluid flow is proportional to the actuation speed. Material selections and package optimization have done to maximize the performance of the cartridge functionality. Different mixing ratio of PDMS (Polydimethylsiloxane) material based on elongation has been tried to select the membrane to seal the reservoir. To contain the reagents inside the reservoir different thermoplastic material has been tried over the elastomer material. Bonding of similar and dissimilar material is studied for fluidic channel layer selection. Extraction of DNA/RNA (Ribonucleic Acid) from blood sample is tried and sufficient quantity of DNA has been extracted from this cartridge for PCR (Polymer Chain Reaction) amplification and detection.

Modeling and characterization of Cu wire bonding process on silicon chip with 45nm node and Cu/low-k structures

Due to the rapid increase of Au price in recent years, there is an emerging trend to use Cu to replace Au in wire bonding because Cu wire not only has lower cost but also has superior electrical, mechanical and thermal properties. However, Cu ball is much harder than Au ball so that there are several challenges for applying Cu wire bond such as excessive deformation of the Al bond pad and dielectric layer crack under the bond pads, especially for low-k structures. In this study, the stress sensors were designed in the test chips and used to measure under pad stress in real-time. Dynamic finite element modeling methodology was developed for wire bonding process and validated by stress measurement. Parametric studies were conducted using numerical modeling to find ways to reduce Al deformation and stresses by adjusting parameters.