Yi-Hung Tsai

Three-dimensional 4F 2 ReRAM cell with CMOS logic compatible process

A new three dimensional vertical bipolar junction transistor (BJT) ReRAM cell with CMOS compatible process is reported. A new logic compatible BJT is vertically formed underneath the resistive stacked film of TiN/Ti/HfO2/TiN as a high performance current driver and bit-cell selector. Using a shallow and tiny NLDD to be an emitter connects with ReRAM film as the bitline, a very thin and self-aligned P-pocket implant to be the wordline, and the N-well is the collector of cells. As a result, the new 3D vertical ReRAM cell is very area-saving and efficiently operated by the high gain (β>50) BJT with a low voltage of 2V for reset and 1.5V for set. By adapting the highly shrinkable 3D BJT current driver in ReRAM, the cell is decoupled with gate length and oxide thickness of logic MOSFETs so that it can be easily scaled down to 4F2 by the lithographic limitation of defining ReRAM film with F2 area.

Reliability evaluation of class-E and class-a power amplifiers with nanoscaled CMOS technology

Circuit reliability of class-E and class-A power amplifiers is investigated based on a newly developed degradation subcircuit model. Measured degradation characteristics on the fabricated circuits agree well with the simulation predictions. Using this model, we have found that the class-E amplifier degrades faster than a class-A amplifier, due to a much higher stress level during switching. With a drastic decrease of PAE, a shorter lifetime is expected for a class-E amplifier.

Three-Dimensional

A new 3-D vertical bipolar junction transistor (BJT) resistive-switching memory (ReRAM) cell with complimentary metal-oxide-semiconductor-compatible process has been demonstrated and characterized. A new logic-compatible BJT is vertically formed underneath the resistive stacked film of TiN/Ti/HfO2/TiN as a high-performance current driver and bit-cell selector. Using a shallow and tiny N-type lightly doped drain to be an emitter connects with ReRAM film as the bitline, a very thin and self-aligned P-pocket implant layer to be the wordline, and the N-well is the collector of the cells. As a result, the new 3-D ReRAM cell is very area saving and efficiently operated by the high-gain (β >; 50) BJT at a low voltage of 2 V for reset and 1.5 V for set. By adapting the highly shrinkable 3-D BJT current driver in ReRAM, the ReRAM is fully decoupled with the gate length and oxide thickness of logic metal-oxide-semiconductor field-effect transistors; furthermore, it can easily be scaled down to 4F2 under the lithographic limitation of defining ReRAM film with F2 area.

\hbox{4F}^{2}

This letter presents a novel differential p-channel logic-compatible multiple-time programmable (MTP) memory cell. This MTP cell has a pair of floating gates, and performs differential read to increase the on/off window. Additionally, a novel self-recovery operation is implemented to boost the floating gate level, thus avoiding the charge-loss problem due to the thin gate oxide requirement in advance logic nonvolatile memory applications. This differential cell with its self-recovery operation is a very promising MTP solution for gate oxide layer with a 70 Å thickness, and can be implemented by 3.3 V I/O in 90 nm and the advanced CMOS logic processes such as 45 nm and beyond.

ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process

A new gateless anti-fuse cell with 45 nm CMOS fully compatible process has been developed for advanced programmable logic applications. This gateless anti-fuse cell processed by pure logic process and decoupled with logic gate oxide has a highly stable and five orders of on/off current window. It also exhibits superior program performance by only 5 V operation with no more than 10 muA programming current. This new nitride gateless anti-fuse cell is a very promising logic OTP solution with fully CMOS compatible process below 90 nm node.

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

This letter presents a new 2-bit/cell contact-gated one-time-programmable (OTP) device, which is demonstrated in a 90-nm CMOS logic process. The cell is programmed by electron injection and storage in the contact-etch-stop-layer (CESL) nitride film. A novel contact gate is introduced to serve as a select transistor, which allows the cell to exhibit good immunity against program and read disturbances. The 2-bit/cell operation is achieved by selectively injecting charges into the CESL on either side of the contact gate through channel-hot-electron operation. With a unit bit area of 13.8 F2 , this nitride-based contact-gated OTP memory is highly feasible for advanced logic applications.

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process

This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 A for 90 nm complementary metal–oxide–semiconductor (CMOS) node and beyond.

A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate

Noise is found to play a beneficial rather than harmful role for neural computation. For example, the sensory neurons exploit stochastic resonance to enhance their sensitivity. This finding has inspired several neuromorphic systems attempting to use noise for computation. Nevertheless, an adaptable noise source is essential for taking the most advantages of noise. This letter presents a resist-protection-oxide (RPO) transistor, which is a defect-rich transistor between the drain implant and the gate. The RPO defects enhance greatly the low-frequency noise of the transistor. The noise level is further adaptable over two decades by the drain voltage. Moreover, the transistor is fully compatible with the standard CMOS logic technology without requiring additional masks or process steps. All the features underpin the development of stochastic neuromorphic computation in integrated circuits.