Yido Koo

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

This paper presents the design of a fully-integrated CMOS frequency synthesizer for PCS- and cellular-CDMA wireless systems. The proposed charge-averaging charge pump scheme suppresses fractional spurs and the VCO combined with coarse tuning improves phase noise characteristics. The improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. Fabricated in 0.35-/spl mu/m CMOS technology, this circuit provides 10 kHz channel spacing with phase noise of -106 dBc/Hz at 100 kHz offset. Power dissipation is 60 mW with 3.0 V supply.

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers and a DC-offset cancellation scheme. The direct conversion scheme combined with a multiphase sampling fractional-N prescaler alleviates the problems of the direct conversion transmitter and receiver. Digital gain control is merged into the baseband filters and variable-gain amplifiers to optimize the linearity of the system, reduce the noise, and improve the sensitivity. Variable-gain amplifiers with DC-offset cancellation loop eliminate the DC-offset in each stage. The chip implemented in 0.35-/spl mu/m CMOS technology shows the experimental results of 6 dBm maximum output power with 38-dB adjacent channel power rejection ratio at 1.92 MHz, 50-dB dynamic range, and 363-mW power consumption in the transmitter. The receiver shows -115.4 dBm sensitivity, a 4.0-dB noise figure, and a dynamic range of 80-dB with 396-mW power consumption.

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.

An image resolution enhancing technique using adaptive sub-pixel interpolation for digital still camera system

An image resolution enhancing technique is described. It is based on extracting 1-dimensional characteristic curves from subsequent frames and sub-pixel displacement values. Through sub-pixel mapping and adaptive interpolation, a high-resolution image can be obtained from several low-resolution image frames. This 1-dimensional algorithm is simple and cost-effective, and can be easily applied in real-time processing for digital still camera application.

A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

This paper describes a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS applications. It is the most important design issue to maximize resource sharing and reuse in designing the multiband transceivers. In particular, reducing the number of voltage-controlled oscillators (VCOs) required for local oscillator (LO) frequency generation is very important because the VCO and phase-locked loop (PLL) circuits occupy a relatively large area. We propose a quad-band GSM transceiver architecture that employs a direct conversion receiver and an offset PLL transmitter, which requires only one VCO/PLL to generate LO signals by using an efficient LO frequency plan. In the receive path, four separate LNAs are used for each band, and two down-conversion mixers are used, one for the low bands (850/900 MHz) and the other for the high bands (1800/1900 MHz). A receiver baseband circuit is shared for all four bands because all of their channel spaces are the same. In the transmit path, most of the building blocks of the offset PLL, including a TX VCO and IF filters, are integrated. The quad-band GSM transceiver that was implemented in 0.25-/spl mu/m CMOS technology has a size of 3.3/spl times/3.2 mm/sup 2/, including its pad area. From the experimental results, we found that the receiver provides a maximum noise figure of 2.9 dB and a minimum IIP3 of -13.2dBm for the EGSM 900 band. The transmitter shows an rms phase error of 1.4/spl deg/ and meets the GSM spectral mask specification. The prototype chip consumes 56 and 58 mA at 2.8 V in the RX and TX modes, respectively.

A fully-integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

This paper presents the design of a fully-integrated CMOS frequency synthesizer for PCS- and cellular-CDMA wireless systems. The proposed charge-averaging charge pump scheme suppresses fractional spurs and the VCO combined with coarse tuning improves phase noise characteristics. The improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. Fabricated in 0.35-/spl mu/m CMOS technology, this circuit provides 10 kHz channel spacing with phase noise of -106 dBc/Hz at 100 kHz offset. Power dissipation is 60 mW with 3.0 V supply.

A semi-digital delay locked loop for clock skew minimization

A two-step approach for fast locking of a DLL (delay-locked-loop) circuit is discussed. The locking process consists of two steps; the coarse tuning in digital domain by tapping a delay position for fast coarse locking, and the accurate phase synchronization between the external clock and the internal clock in analog operation mode. With this two step approach, fast locking and low phase error can be simultaneously achieved.

A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.

Full-CMOS 2.4 GHz wideband CDMA transmitter and receiver with direct conversion mixers and DC-offset cancellation

The proposed direct conversion scheme combined with a multi-phase sampling fractional-N prescaler offers solutions to problems of a direct conversion transmitter and receiver. In the experimental results, the transmitter shows 0 dBm maximum output power with 38 dB ACPR at 0.5 BW, 50 dB dynamic range, and 363 mW power consumption. The receiver shows -115.4 dBm sensitivity, 4.0 dB noise figure, and 80 dB dynamic range with 396 mW power consumption.