Hyungki Huh
Seoul National University
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Featured researches published by Hyungki Huh.
IEEE Journal of Solid-state Circuits | 2002
Yido Koo; Hyungki Huh; Yongsik Cho; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim
This paper presents the design of a fully-integrated CMOS frequency synthesizer for PCS- and cellular-CDMA wireless systems. The proposed charge-averaging charge pump scheme suppresses fractional spurs and the VCO combined with coarse tuning improves phase noise characteristics. The improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. Fabricated in 0.35-/spl mu/m CMOS technology, this circuit provides 10 kHz channel spacing with phase noise of -106 dBc/Hz at 100 kHz offset. Power dissipation is 60 mW with 3.0 V supply.
international solid-state circuits conference | 2004
Hyungki Huh; Young-Ho Koo; Kang-yoon Lee; Yeonkyeong Ok; Sungho Lee; Daehyun Kwon; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim
A fully integrated dual-band frequency synthesizer in 0.35 /spl mu/m CMOS technology achieves a phase noise of -141 dBc/Hz at 1.25 MHz offset in the PCS band with a reference frequency doubler. Fractional spurs are reduced by 8.6 dB at 50 kHz offset with a replica compensated charge pump.
IEEE Journal of Solid-state Circuits | 2005
Hyungki Huh; Yido Koo; Kang-yoon Lee; Yeonkyeong Ok; Sungho Lee; Daehyun Kwon; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wootae Kim
The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.
Archive | 2002
Hyungki Huh; Eunseok Song; Kang Yoon Lee; Yido Koo; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee
Archive | 2001
Jeong-Woo Lee; Yido Koo; Kang Yoon Lee; Eunseok Song; Hyungki Huh; Joonbae Park; Kyeongho Lee
Archive | 2004
Yido Koo; Hyungki Huh; Kang Yoon Lee; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee
Archive | 2004
Yido Koo; Hyungki Huh; Kang Yoon Lee; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee
Archive | 2004
Yido Koo; Hyungki Huh; Kang Yoon Lee; Jeong-Woo Lee; Joonban Park; Kyeongho Lee
Archive | 2004
Yido Koo; Hyungki Huh; Kang Yoon Lee; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee
Archive | 2004
Yido Koo; Hyungki Huh; Kang Yoon Lee; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee