Yoshifumi Ikenaga

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.

High-speed InP/InGaAs DHBTs with ballistic collector launcher structure

We demonstrate high-speed InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with significantly improved collector carrier transport. The proposed collector design scheme allows for using moderate collector thickness to achieve high f/sub max/ (/spl sim/300 GHz) while maintaining high f/sub T/ (/spl sim/200 GHz). The DHBTs will meet the demand of ultra-high-speed applications for both high f/sub T/ and high f/sub max/.

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

We have developed a circuit for determining an optimal supply voltage, VOPT, for which energy consumption will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and operation time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT with high accuracy. VOPT operations with power gating at 40 MHz, and where VDD = 0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency). Further, we propose a scheme for suppressing determination error, one that results in voltage error of less than 50 mV.

Monitoring scheme for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes a newly developed monitoring scheme for minimizing power consumption by means of supply voltage V/sub DD/ and threshold voltage V/sub TH/ dynamic control in active and standby modes. In the active mode, on the basis of delay monitoring results, either V/sub DD/ control or V/sub TH/ control is selected to avoid any oscillation problem between them. Switching current I/sub SW/ and leakage current I/sub LEAK/ are monitored, and V/sub TH/ is adjusted so as to maintain that ratio known to indicate minimum power consumption. In the standby mode, the precision of optimum body bias monitoring is improved by taking into consideration the effects of lowered V/sub DD/ and gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that the proposed scheme results in successful I/sub SW//I/sub LEAK/ ratio maintenance and successful detection of optimum body bias conditions (I/sub OFF/ = I/sub SUB/ (= GIDL + I/sub GB/)) to within 20% of actual minimum leakage current values.

Fast voltage control scheme with adaptive voltage control steps and temporary reference voltage overshoots for dynamic voltage and frequency scaling

We have developed a voltage control scheme to reduce control time using a delay monitor and step-by-step supply-voltage control. With this scheme, voltage control steps are adaptively controlled, and there are temporary overshoots in the reference voltage. Experimental results with a 65-nm CMOS device indicate that the adaptive voltage control steps successfully reduce the voltage control time by about 35 % over that with fixed step. Simulation results indicate that temporary reference voltage overshoots reduce control time by more than 50%. The combination of these schemes is also effective for control time reduction.

An Optimal Supply Voltage Determiner Circuit for Minimum Energy Operations

We have developed a circuit for determining an optimal supply voltage, VOPT for which energy consumption in circuit operations will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and delay time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT within 3% of actual minimum energy consumption. VOPT operations with power gating at 40 MHz, and where VDD=0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency).

Characterization of InP/InGaAs Heterojunction Bipolar Transistors with Carbon-Doped Base Layers Grown by Metal-Organic Chemical Vapor Deposition and Molecular Beam Epitaxy

We characterized InP/InGaAs heterojunction bipolar transistors (HBTs) with carbon-doped InGaAs base layers grown by metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). Since HBTs grown using these techniques require different processing steps, resulting in different types of process-related damage, we analyzed the bulk and periphery components of DC characteristics to clarify the effects of the crystal growth and process techniques on device characteristics separately. The MBE-grown HBTs were found to have an advantage over the MOCVD-grown HBTs, because they do not require harmful high-temperature annealing during processing steps. On the other hand, it was also shown that the MOCVD-grown HBTs have a significantly lower base recombination rate than the MBE-grown HBTs, making MOCVD a suitable method of growing InP HBTs that do not require annealing, such as that with a GaAsSb base.

Delay and Power Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage VDD and threshold voltage VTH in active and standby modes. On the basis of delay monitoring results, either VDD control or VTH control is selected, in order to avoid any oscillation problem between them in the active mode. With respect to power monitoring, experimental results with a 90-nm CMOS device show that it reduces power consumption by making it possible (1) to maintain a certain switching current ISW / leakage current ILEAK ratio in the active mode, and (2) to detect optimum body bias conditions (subthreshold current ISUBTH = substrate current ISUB) within an error of less than 20 % with respect to actual minimum leakage current values in the standby mode