Yogesh K. Ramadass

A Battery-Less Thermoelectric Energy Harvesting Interface Circuit With 35 mV Startup Voltage

A battery-less thermoelectric energy harvesting interface circuit to extract electrical energy from human body heat is implemented in a 0.35 CMOS process. A mechanically assisted startup circuit enables operation of the system from input voltages as low as 35 mV. An efficient control circuit that performs maximal transfer of the extracted energy to a storage capacitor and regulates the output voltage at 1.8 V is presented.

A 65nm Sub-V t Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter

This paper presents a 65nm sub-Vt SoC featuring a microcontroller core and custom 128Kb SRAM functional in sub-threshold, powered by a switched capacitor DC-DC converter that delivers variable load voltages from 0.3V to 0.6V.

An efficient piezoelectric energy-harvesting interface circuit using a bias-flip rectifier and shared inductor

Energy harvesting is an emerging technology with applications to handheld, portable and implantable electronics. Harvesting ambient vibration energy through piezoelectric (PE) means is a popular energy harvesting technique that can potentially supply 10 to 100s of µW of available power [1]. One of the limitations of existing PE harvesters is in their interface circuitry. Commonly used full-bridge rectifiers and voltage doublers [2] severely limit the electrical power extractable from a PE harvesting element. Further, the power consumed in the control circuits of these harvesters reduces the amount of usable electrical power. In this paper, a bias-flip rectifier that can improve upon the power extraction capability of existing full-bridge rectifiers by up to 4.2× is presented. An efficient control circuit with embedded DC-DC converters that can share their filter inductor with the bias-flip rectifier thereby reducing the volume and component count of the overall solution is demonstrated.

Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications

This paper presents a voltage scalable switched capacitor (SC) DC-DC converter which employs on-chip charge- transfer capacitors. The DC-DC converter makes use of multiple topologies to achieve scalable voltage generation while minimizing conduction loss and a technique called divide-by-3 switching to minimize the loss due to bottom-plate parasitics. It also uses automatic frequency scaling to reduce switching losses. The converter employs an all digital control which consumes no static power. The voltage scalable SC DC-DC converter with integrated on-chip charge-transfer capacitors was implemented in a 0.18 mum CMOS process and achieves above 70% efficiency over a wide range of load powers from 5 muW to 1 mW, while delivering load voltages from 300 mV to 1.1 V. The active area consumed by the converter is 0.57 mm2.

A 65 nm Sub-

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.

V_{t}

Implementing efficient and cost-effective power regulation schemes for battery-powered mixed-signal SoCs is a key focus in integrated circuit design. This paper presents a fully-integrated switched-capacitor DC-DC converter in 45 nm digital CMOS technology. The proposed implementation uses digital capacitance modulation instead of traditional PFM and PWM control methods to maintain regulation against load current changes. This technique preserves constant frequency switching while also scaling switching and bottom-plate losses with changes in load current. Therefore, high efficiency can be achieved across different load current levels while maintaining a predictable switching noise behavior. The converter occupies only 0.16 mm2, and operates from 1.8 V input. It delivers a programmable sub-1 V power supply with efficiency as high as 69% and load current between 100 μA and 8 mA. Measurement results confirm the theoretical basis of the proposed design.

Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

Minimizing the energy consumption of battery-powered systems is a key focus in integrated circuit design. This paper presents an energy minimization loop, with on-chip energy sensor circuitry, that can dynamically track the minimum energy operating voltage of arbitrary digital circuits with changing workload and operating conditions. An embedded DC-DC converter which enables this minimum energy operation is designed to deliver load voltages between 0.25 V to 0.7 V. The minimum energy tracking loop along with the DC-DC converter and test circuitry were fabricated in a 65 nm CMOS process. The area overhead of the control loop is only 0.05 mm2. Measured energy savings of the order of 50%-100% are obtained on tracking the minimum energy point (MEP) as it varies with workload and temperature. The DC-DC converter delivers load voltages as low as 250 mV and achieved an efficiency >80% while delivering load powers of the order of 1 muW and higher from a 1.2 V supply.

A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS

Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multi-media to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit micro-controller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter.

Minimum Energy Tracking Loop With Embedded DC–DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS

Emerging microsystems such as portable and implantable medical electronics, wireless microsensors and next-generation portable multimedia devices demand a dramatic reduction in energy consumption. The ultimate goal is to power these devices using energy harvesting techniques such as vibration-to-electric conversion or through wireless power transmission. A major opportunity to reduce the energy consumption of digital circuits is to scale supply voltages to 0.5V and below. The challenges associated with ultra-low-voltage design will be presented. These include variation-aware design for logic and SRAM circuits, efficient DC-DC converters for ultra-low-voltage delivery, and algorithm structuring to support extreme parallelism. This paper also addresses micro-power analog and RF circuits, which require the use of application-specific structures and highly digital variation-aware architectures.

Technologies for Ultradynamic Voltage Scaling

Digital baseband processors [1] in portable devices today are able to operate off voltages of 1V and less. Efficient DC-DC converters are required to power these ICs from Li-ion batteries with a voltage range of 2.8 to 4.2V. This is done by a discrete power management IC (PMIC) capable of handling the high battery voltage. However, there is significant push in integrating the PMIC module with the baseband processor implemented in scaled technologies thereby reducing the number of system-level components. This paper presents the circuit techniques used in a 45nm CMOS DC-DC converter with high battery-voltage handling capability.