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Dive into the research topics where Yohtaro Umeda is active.

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Featured researches published by Yohtaro Umeda.


Japanese Journal of Applied Physics | 1994

0.05-μm-Gate InAlAs/InGaAs High Electron Mobility Transistor and Reduction of Its Short-Channel Effects

Takatomo Enoki; Masaaki Tomizawa; Yohtaro Umeda; Yasunobu Ishii

In this paper, we discusse the advantages of thinning the channel on short-channel effects for lattice-matched InAlAs/InGaAs high electron mobility transistors (HEMTs) with sub-0.1-µm-long gates with regard to the performance of a 0.05-µm-gate device. To fabricate a sub-0.1-µm gate, the opening shape of the gate-footprint is controlled by using a bilayer dielectric film system and RIE side etching. The device shows a current gain cutoff frequency of 300 GHz and g m/g d ratio of 15. Thinning the channel and the barrier down to 100 A improves carrier confinement and subthreshold characteristics and is indispensable for reducing the short-channel effects in the sub-0.1-µm-gate-length region.


Japanese Journal of Applied Physics | 1998

ULTRAHIGH-SPEED INTEGRATED CIRCUITS USING INP-BASED HEMTS

Takatomo Enoki; Haruki Yokoyama; Yohtaro Umeda; Taiichi Otsuji

The device technologies for 0.1-µm-gate InP-based high electron mobility transistors (HEMTs), which consist of an InAlAs/InGaAs modulation-doped structure on an InP substrate, are described. They yielded a current gain cutoff frequency (fT) of over 180 GHz and a transconductance (gm) of over 1 S/mm in circuits. An InP recess-etch stopper improved the uniformity of threshold voltage and enabled us to apply HEMTs in digital ICs. A diode consisting of an InAlAs Schottky junction is monolithically integrated with a HEMT and used as a level shifter in digital ICs. By combining novel circuit technologies and the HEMT-IC technologies, the maximum operation speed of IC has been pushed up to over 40 Gbit/s. As a benchmark for future large-capacity networks, electrically multiplexed and demultiplexed 40 Gbit/s, 300 km transmission was successfully demonstrated using the device technologies described here.


ieee gallium arsenide integrated circuit symposium | 1997

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

Taiichi Otsuji; Koichi Murata; Takatomo Enoki; Yohtaro Umeda

We report on an 80-Gbit/s 2:1 selector-type multiplexer IC using InAlAs/InGaAs/InP HEMTs incorporating a high-speed double layer interconnection process with a low permittivity insulator. The record operating data rate was measured on a 3-inch wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time.


IEEE Transactions on Microwave Theory and Techniques | 1996

Loss-compensated distributed baseband amplifier IC's for optical transmission systems

Shunji Kimura; Yuhki Imai; Yohtaro Umeda; Takatomo Enoki

We describe a distributed baseband amplifier using a new loss compensation technique for the drain artificial line. The new loss compensation circuit improves a high-frequency performance of the amplifier and makes the gain bandwidth product of the amplifier larger than that of conventional ones. We also use dc matching terminations and dumping resistors for the gate and drain artificial lines to obtain flat gain from frequencies as low as 0 Hz. One IC fabricated using 0.1 /spl mu/m-gatelength InAlAs/InGaAs/InP HEMTs has a gain of 16 dB over a 0-to-50 GHz band, resulting in a gain bandwidth product of about 300 GHz. Another IC has a gain of 10 dB over a 0-to-90 GHz band. These are the highest gain bandwidth product and the widest band reported for baseband amplifier ICs applicable to optical transmission systems.


IEEE Transactions on Electron Devices | 1999

High-performance 0.1-/spl mu/m gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology

Tetsuya Suemitsu; Haruki Yokoyama; Yohtaro Umeda; T. Enoki; Yasunobu Ishii

Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMTs (E-HEMTs) is described for the first time. Most important issue for the fabrication of E-HEMTs is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 /spl Omega//spl middot/mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-/spl mu/m gate E-HEMTs. This is therefore one of the promising devices for ultra-high-speed applications.


ieee gallium arsenide integrated circuit symposium | 1996

40-Gbit/s ICs for future lightwave communications systems

Taiichii Otsuji; Yuhki Imai; Eiichi Sano; Shunji Kimura; Satoshi Yamaguchi; Mikio Yoneyama; Takatomo Enoki; Yohtaro Umeda

This paper reviews recent advances in 40-Gbit/s class analog and digital ICs developed at our laboratories for future lightwave communications systems. A 0.1-/spl mu/m gate InAlAs/InGaAs HEMT with InP recess etch stopper was adopted mainly for IC fabrication. Fabricated ICs demonstrate excellent data-multiplexing, demultiplexing and amplifying operation at 40 Gbit/s.


Japanese Journal of Applied Physics | 1995

Measurement of High-Frequency Dielectric Characteristics in the mm-Wave Band for Dielectric Thin Films on Semiconductor Substrates.

Kenji Ikuta; Yohtaro Umeda; Yasunobu Ishii

Using dielectric thin film capacitors and devices specially designed for correcting stray effect around the capacitors, the dielectric constant and dielectric loss up to 50 GHz can be successfully measured by the reflection coefficient measured with a network analyzer. The high-frequency characteristics are consistent with low-frequency characteristics measured with an LCR bridge. The relative error between the high-frequency and the low-frequency is estimated to be within 10%. The method is a practical way to obtain the characteristics of dielectric thin films accurately and quickly in final form.


international solid-state circuits conference | 2005

1.25 Gb/s burst-mode receiver ICs with quick response for PON systems

Makoto Nakamura; Yuhki Imai; Yohtaro Umeda; Jun Endo; Yuji Akatsu

This paper describes burst-mode receiver ICs with quick response for 1.25-Gb/s optical access networks. In a point-to-multipoint fiber access system, such as a passive optical network (PON) system, the receiver should be able to handle burst-data packets with different amplitudes. In burst-mode transmission, a receiver with a quick response is desired for high efficiency in data transmission. In addition, high sensitivity is also required for such a shared access system. To achieve a quick response and high sensitivity at the same time, a transimpedance amplifier (TIA) with three gain modes has been designed. The use of a hysteresis comparator enables fast gain mode switching. A limiting amplifier with feed-forward auto-offset compensation (AOC) is also used for quick response to burst data. These circuit techniques require no external adjustment. Using these design techniques, optical receiver ICs were fabricated in SiGe-BiCMOS technology. The optical receiver built with the ICs exhibits a settling time of under 20 bits and a sensitivity of -30 dBm with wide dynamic range of over 26 dB using a p-i-n photodiode (PD) for burst-mode optical input at 1.25 Gb/s. These fast-response receiver chips improve the data transmission efficiency. The use of a conventional p-i-n PD and the freedom from external adjustment make it possible to build an inexpensive receiver.


IEEE Microwave and Guided Wave Letters | 1994

A DC to 38-GHz distributed analog multiplier using InP HEMT's

Y. Imai; Shunji Kimura; Yohtaro Umeda; Takatomo Enoki

A novel distributed analog multiplier is proposed. It employs Gilbert cells as the unit section of the distributed structure. The single-ended analog multiplier MMICs are built using 0.1-/spl mu/m-gate-length InP HEMTs and uniplanar technology. The conversion gain is about -5 dB with LO power of 10 dBm, RF and IF 3-dB bandwidths are 38 and 16 GHz, respectively.<<ETX>>


international electron devices meeting | 1998

30-nm-gate InAlAs/InGaAs HEMTs lattice-matched to InP substrates

T. Suemitsu; Tetsuyoshi Ishii; Haruki Yokoyama; Yohtaro Umeda; Takatomo Enoki; Yasunobu Ishii; Toshiaki Tamamura

In this paper, we report the fabrication and the device characteristics of the InP-based lattice-matched HEMTs with a 30-nm gate, which is the smallest gate yet achieved for InP-based HEMTs. A fullerene-incorporated nanocomposite resist is used in electron beam (EB) lithography to achieve such a small gate. A cutoff frequency of the 30-nm-gate HEMTs is 350 GHz, which is comparable to the reported value for 50-nm-gate InP-based pseudomorphic HEMTs and one of the highest value achieved by any kind of three-terminal electronic device.

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Takatomo Enoki

Nippon Telegraph and Telephone

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T. Enoki

Nippon Telegraph and Telephone

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Haruki Yokoyama

Nippon Telegraph and Telephone

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Koichi Murata

Nippon Telegraph and Telephone

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Yuhki Imai

Nippon Telegraph and Telephone

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