Yonah Cho

Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks

S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in FinFET devices for the 22nm node and remain effective with conservative scaling of contact / gate CD only.

Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability

Two approaches to top-surface nitridation of tunnel oxide, i.e., rapid thermal nitridation using NH3 anneal and decoupled plasma nitridation, are compared. Floating-gate MOS capacitors with source/drain were used to evaluate Flash memory performance and reliability. Tunnel-oxide NH3 anneal degrades postcycling retention performance compared to plasma nitridation for the same equivalent oxide thickness reduction. The poorer performance of NH3 anneal is related to higher N incorporation into SiO2 bulk rather than top surface. Postcycling memory erase-level shift and memory window (MW) closure is lower for plasma nitridation compared to NH3 anneal. A new integration scheme using plasma nitridation followed by NO anneal produces the lowest MW closure with cycling.

A study of low energy phosphorus implantation and annealing in Si:C epitaxial films

The effect of phosphorus implantation and thermal annealing on properties of Si:C epitaxial films was investigated. High resolution x-ray diffraction analysis and secondary ion mass spectroscopy indicated that spike annealing only causes slight loss of substitutional carbon. Phosphorus implantation, even with low energy, could cause surface damages and loss of substitutional carbon. Although spike annealing effectively activates implanted phosphorus, it also results in significant substitutional carbon loss (from 1.2% to less than 0.5%) within the phosphorus diffused layer. The interaction of carbon and phosphorus resulted in a junction profile as abrupt as with 3 nm/decade.

Experimental and Theoretical Analysis of Dopant Diffusion and C Evolution in High-C Si:C Epi Layers: Optimization of Si:C Source and Drain Formed by Post-Epi Implant and Activation Anneal

A comprehensive physics based calibrated model was developed to explain the observed n-type dopant diffusion and substitutional carbon (Csub) evolution in high C (>1%) Si:C epitaxial films. Both experimentally and theoretically, we demonstrated a viable doping scheme with near 100% Csub retention using undoped Si:C epi with post-epi implant and optimized anneal.

Effective Surface Treatments for Selective Epitaxial SiGe Growth in Locally Strained pMOSFETs

Cyclical wet clean in DI-O 3 /SC1/DHF and low temperature bake in HCl/H 2 are presented as effective surface treatments for selective SiGe epitaxial deposition used to fabricate embedded SiGe pMOSFETs. The presented methods are most effective for device structures under limited chemical and thermal budgets.

Integrating Selective Epitaxy in Advanced Logic & Memory Devices

INTRODUCTION Selective epitaxy has gained increasing momentum in advanced high-performance logic as well as volatile and nonvolatile memory device fabrication. The advantages of this technique range from the well documented application of strained SiGe epitaxial films used to increase hole mobility and performance in pFET devices to intrinsic Si epitaxial layers used to prevent short channel effects in memory devices (DRAM). Other applications call upon the time tested strengths of epitaxy in ensuring abrupt, activated doped layers or junctions without the defectivity associated with implanted profiles.

Effectiveness of Si Seed for Selective SiGe Epitaxial Deposition in Recessed Source and Drain for Locally Strained pMOS Application

A thin layer (15A) of Si seed was employed to help nucleate low temperature selective SiGe epitaxial film in recessed source and drain. In combination with pre-epi wet clean and low temperature chemical bake, use of Si seed resulted in improved SiGe film morphology and micro-loading effect, and further improved dislocation on the lateral recess interface. Introduction Locally strained Si technology using embedded SiGe has demonstrated improved pMOSFET device performance through hole mobility enhancement [1-3]. Widely used, embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si source and drain in the pMOSFET area. Typical process steps for recessed source and drain SiGe flow is described elsewhere [2]. Prior to selective SiGe epi growth, multiple implants and dry etch of source and drain result in surface damage and chemical residues. Surface quality and cleanliness of the etched Si surfaces have great impact on the morphology and SiGe film quality. Typically, wet clean (in diluted HF) or high temperature bake (> 800 °C) is used as a preepi step to remove surface C and O. Previous study [4] indicated improvement of SiGe film morphology by multiple cycles of wet clean in ozonated DI/SC1/DHF. For most harsh surfaces with severe damage casued by implant and dry etch, use of Si seed layer is employed to nucleate uniform SiGe film with good quality and to minimize micro-loading effect. Experiments and Results Prior to SiGe deposition, device wafers were cleaned in ozonated DI, SC1, and dipped in diluted HF (DHF). Wafers were introduced to the reaction chamber for low temperature bake followed by selective deposition of Si seed and SiGe film in recessed source and drain areas in the pMOS area. Control wafer was process with similar pre-epi wet clean, bake, and deposition without the seed layer. Wafers with severe surface damage did not yield SiGe film growth of good morphology without the seed layer. However, wafers with surface damage resulted in difference in SiGe film morphology with or without the Si seed as shown in Figure 1 and Figure 2. Improved surface morphology is observed as clear faceting and dislocation free around the lateral recess interface in the case with the Si seed. Also, the surface roughness can be healed well in the different density area of wafer by Si seed, further improve micro-loading with the similar incubation time. Micro-loading between isolated area and dense area was improved 92% once Si seed layer was applied. Besides, Si seed implement not only decrease micro-loading effect but also without SiGe quality degradation. Micro-loading was defined as (maximum thickness-minimum thickness)/minimum thickness in the same die. (a) (b) Figure 1. Comparison of morphology of selective grown SiGe film (a) with and (b) without Si seed.

Quality and reliability of oxide by low thermal budget rapid thermal oxidation

In order to meet increasing requirement for low thermal budget oxidation in memory and logic applications, RadOx™, previously known as in-situ steam generation (ISSG) oxidation, processes of low thermal budgets were developed. In this paper, oxides obtained by 700°C soak and 900–1050°C spike RadOx™ processes are presented. Sidewall growth behavior in STI-type structures were characterized and showed no bird’s beak encroachment by the developed oxidation processes. Basic bulk oxide (40Å) integrity and reliability characteristics were compared to the 1050°C soak RadOx™ reference. Using planar metal-on-semiconductor (MOS) capacitors as the test vehicles, flat-band voltage (V<inf>fb</inf>), interface trap density (D<inf>it</inf>), leakage current, and stress-induced leakage current (SILC) were measured. V<inf>fb</inf> shift of less than 20mV and D<inf>it</inf> less than 2×10¹¹/cm² were observed from the low temperature soak and spike oxides. Leakage currents from fresh devices and after high current stressing (0.1A/cm²) were comparable to the reference oxide.

A Study of Low Energy Phosphorus Implantation and Annealing in Si:C Epitaxial Films

We investigated the effect of dopant implantation and thermal annealing on substitution carbon concentration of Si:C epitaxial film. While spike annealing at T=1050 degC results in slight loss of substitution carbon (0.6%) but maintains high crystalline, phosphorus implantation induces significant loss of substitution carbon and a change of carbon depth profile. It is also observed that very abrupt junction can be formed in a Si:C epitaxial film