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Dive into the research topics where Yong Kong Siew is active.

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Featured researches published by Yong Kong Siew.


symposium on vlsi technology | 2005

Integration of a poisoning-free dual damascene CDO film stack for 90 nm & beyond low-k BEOL

Wu Ping Liu; J.B. Tan; Wei Lu; Shyam Pal; Yong Kong Siew; Hai Cong; Bei Chao Zhang; Xian Bin Wang; Fan Zhang; Liang Choo Hsia

In this paper we report on the successful integration of a 90nm low-k full VIA-first dual damascene process architecture using carbon-doped-oxide (CDO) and SiC etch-stop-layer (ESL). One of the key features of the integration scheme is that the effects of photoresist poisoning have been eliminated by optimization of the low-k (k < 3.0) film stack deposition process. The mechanisms underlying photoresist poisoning have been investigated through detailed partition studies. Electrical yield and reliability data will be shown to demonstrate the performance of the overall integration approach.


Archive | 2000

Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures

Seng Keong Victor Lim; Young-Way Teh; Ting-Cheong Ang; Alex See; Yong Kong Siew


Archive | 2006

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

Johnny Widodo; Bei Chao Zhang; Tong Qing Chen; Yong Kong Siew; Fan Zhang; San Leong Liew; John Sudijono; Liang Choo Hsia


Archive | 2004

Method to control dual damascene trench etch profile and trench depth uniformity

Hai Cong; Yong Kong Siew; Liang Choo Hsia


Archive | 2008

Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement

Beichao Zhang; Johnny Widodo; Juan Boon Tan; Yong Kong Siew; Fan Zhang; Haifeng Sheng; Wenhe Lin; Young Way Teh; Jinping Liu; V. Ho; Liang Choo Hsia


Archive | 2008

Interconnections for integrated circuits including reducing an overburden and annealing

Lup San Leong; Yong Kong Siew; Liang Choo Hsia


Semiconductor international | 2003

Trench etch: Optimization with 193 nm resist

Yong Kong Siew; Raymond Joy; Dennis Tan; Wuping Liu; Ravi Srivastava; Juan Boon Tan; Liang-Choo Hsia


Archive | 2008

Method for corrosion prevention during planarization

Fan Zhang; Lup San Leong; Yong Kong Siew; Bei Chao Zhang


Copper interconnects, new contact metallurgies/structures, and low-k interlevel dielectrics | 2003

A novel approach for dual damascene trench etch for 90nm low-K interconnect with no middle etch stop layer

Tong Qing Chen; Hai Cong; Wu Ping Liu; Yong Kong Siew; Yelehanka Ramachandramurthy Pradeep; Liang Choo Hsia; Rakesh Jaiswal; Alok Jain; Ivan Sim


Archive | 2001

Verfahren zur Hestellung von Zwischenmetall-Dielektrikanwendungen mit Luftspalten zwischen Metall-Leitern

Ting-Cheong Ang; Victor Seng Keong Lim; Alex See; Yong Kong Siew; Young-Way Teh

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Liang Choo Hsia

Chartered Semiconductor Manufacturing

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Fan Zhang

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Alex See

Chartered Semiconductor Manufacturing

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Bei Chao Zhang

Chartered Semiconductor Manufacturing

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Hai Cong

Chartered Semiconductor Manufacturing

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Ting-Cheong Ang

Chartered Semiconductor Manufacturing

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Young-Way Teh

Chartered Semiconductor Manufacturing

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Johnny Widodo

Chartered Semiconductor Manufacturing

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Juan Boon Tan

Chartered Semiconductor Manufacturing

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Lup San Leong

Chartered Semiconductor Manufacturing

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