Bei Chao Zhang

TDDB robustness of highly dense 65NM BEOL vertical natural capacitor with competitive area capacitance for RF and mixed-signal applications

The integration of vertical natural capacitors (VNCap) into existing backend-of-line (BEOL) stacks is an important aspect to enable radio-frequency and mixed signal features without extra mask costs. From manufacturing and reliability point of view these devices can be rather challenging since they may contain millions of vias and meters of metal interconnects. In this paper we will discuss the robustness of densely packed vertical natural capacitors against time dependent dielectric breakdown (TDDB) with respect to both intrinsic and extrinsic aspects. The intrinsic TDDB of VNCap is sensitively influenced by the design aspects that change the physical spacing within the metal pattern. A strong trade-off between area capacitance and intrinsic TDDB was observed. If the tested VNCap area is large enough, early failures were systematically detected with a certain probability. We will discuss a method that allows the modelling of an early thinning mode due to unavoidable spacing variations within the patterns. Based on this method a criterion is derived to distinguish between early fails that can still be tolerated and extrinsic defects of gross nature that are critical. Furthermore we will present observations on the influence of BEOL process aspects on intrinsic TDDB performance and extrinsic defect density such as CMP slurry and overpolish or time delay after trench etch and copper CMP.

Stress-induced voiding in multi-level copper/low-k interconnects

Stress-induced voiding phenomenon in vias at different metallization layers was studied in details with stress temperatures ranging from 150/spl deg/C to 300/spl deg/C. At 1000-hour of stress migration (SM) test, the percentage change in the resistance showed that the thermally induced stress in the vias increased with increasing metallization layers. Furthermore, the vias at the edge of the wafer were more sensitive to the thermally induced stress than that at the center of the wafer. As such, more stress-induced damaged vias were observed at the upper metallization layers and at the edge of the wafer. These phenomena were attributed to the accumulated compressive stress experienced by the wafer with each increasing metallization layer and the poorer diffusion barrier coverage at the edge of the wafer due to the nature of physically vapor deposition (PVD) process. Some strategies such as the implementation of a resputtering step during the PVD process of the diffusion barrier layer and the design of dual-via interconnect were demonstrated to be effective in managing the stress-induced voiding effect in Cu interconnects. It was also proven that re-sputtering step during the PVD process of the diffusion barrier layer was necessary when Cu was integrated with dielectric of lower constant values because of its stronger dependency on process.

Effect of chemical mechanical polishing scratch on TDDB reliability and its reduction in 45nm BEOL process

The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB failure samples matches well with the defect wafer map from bright field scans. Electrical fault isolation using thermally induced voltage alteration (TIVA) analysis is employed to locate the hot spot where TDDB leakage occurs. Polish scratchinduced metal damage at the hot spot is further analyzed by topdown scanning electron microscopy (SEM) after de-processing. Also, the depth of the polish scratch is confirmed by using transmission electron microscopy (TEM) analysis. It clearly shows that the embedded particle on copper (Cu) surface and the liner damage resulted from polish scratch severely affect the TDDB reliability. In-situ CMP platen3 (P3) pad chemical preclean is found to reduce the polish scratch density effectively and significantly improve the V-ramp/TDDB reliability performance. However, inappropriate usage of chemical pre-clean would cause Cu corrosion and lead to EM degradation. Hence, a balance between polish scratch reduction and Cu corrosion associated with P3 pad pre-clean needs to be achieved.

BEOL Advance Interconnect Technology Overview and Challenges

An overview of the semiconductor roadmap of interconnects process transition from 0.13mum to 45nm using current proven state- of-the-art manufacturing technology in relation to the integration of dielectric material progressing from fluorinated silica glass to porous low-k will be discussed. Key challenges of process integration with shrinking dimension to meet the ever-demanding timing delay due to interconnects will be shown. Process enhancements with design for manufacturing concepts are addressed to meet the industrial specifications of reliability and chip package interaction for mass production.

Integration of a poisoning-free dual damascene CDO film stack for 90 nm & beyond low-k BEOL

In this paper we report on the successful integration of a 90nm low-k full VIA-first dual damascene process architecture using carbon-doped-oxide (CDO) and SiC etch-stop-layer (ESL). One of the key features of the integration scheme is that the effects of photoresist poisoning have been eliminated by optimization of the low-k (k < 3.0) film stack deposition process. The mechanisms underlying photoresist poisoning have been investigated through detailed partition studies. Electrical yield and reliability data will be shown to demonstrate the performance of the overall integration approach.