Yong-Xiao Chen

Fault modeling and testing of 1T1R memristor memories

Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

Test cost optimization technique for the pre-bond test of 3D ICs

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

A built-in self-test scheme for classifying refresh periods of DRAMs

A DRAM with multiple-refresh-period (MRP) method is one of effective refresh power reduction techniques. To support the MRP method, effective test methods for classifying the refresh period of each DRAM block are needed. In this paper, we propose an effective test method for classifying the refresh periods of DRAM blocks. Also, a programmable built-in self-test (BIST) scheme being able to support the test method is proposed.

Fault modeling and testing of resistive nonvolatile-8T SRAMs

In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast poweron speed. A Rnv8T SRAM cell is composed of a 6T SRAM cell, two resistive devices, and two transistors. In this paper, we define several memristor-related faults for the Rnv8T SRAM considering electrical defects. Also, a March-like test algorithm which can cover simple SRAM faults and defined memristor-related faults are proposed. In comparison with the existing work, the proposed March-like test needs longer test time, but provides better fault coverage on the targeted faults.

A built-in method for measuring the delay of TSVs in 3D ICs

This paper proposes a built-in delay measurement (BIDM) technique to measure the delay of through-silicon via (TSV) in the phase of post-bond test. The BIDM circuit can be shared by multiple TSVs such that the area overhead of the BIDM circuit is minimized. Furthermore, a measurement flow is proposed to eliminate the delay of interconnection between two TSVs such that the BIDM accuracy is not worsened with the increased number of measured TSVs. Experimental results show that the deviation of the result of BIDM and Hspice simulation is about 2.7%. Furthermore, a low-cost delay measurement element is proposed. In comparison with a typical Vernier delay line, the proposed delay measurement element can achieve 18% area reduction. In comparison with the ring-oscillator-based delay measurement method, the proposed BIDM has the features of low error and low cost, but needs long measurement time.

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories

Memristor is a resistive device which is considered as an alternative non-volatile device for future non-volatile memories. For a memristor memory, a reference current is needed for discriminating the high-resistance (ROFF) state from low-resistance (RON) state. The reference current has an impact on the yield and reliability of the memristor memory. In this paper, we propose a test method in associate with a current comparing circuit for finding the boundary currents of ROFF and RON states. Therefore, the user can set a good reference current according to the boundary currents. Simulation results show that if our test method is used to identify the boundary currents, 2.05% and 3.68% memristor cells which may be read incorrectly due to process variation for ROFF/RON = 50 and 3 can be eliminated, respectively.

Testing Inter-Word Coupling Faults of Wide I/O DRAMs

Wide-I/O dynamic random access memory (wide I/O DRAM) is one of promising solutions to increase the memory bandwidth. Similar to modern double-data-rate DRAMs, the minimum burst length of wide I/O DRAM is at least two. Thus, either a read or a write operation is executed, two words will be read or written at least each time. This causes that the testing of inter-word coupling faults becomes complicated. In this paper, we propose a method to modify conventional March tests into modified March tests which can fully cover inter-word coupling faults of wide I/O DRAMs with minimum burst length of two and programmable burst order. Furthermore, the test complexity of modified March tests for different burst lengths is analyzed. Results show that the test time of modified March tests is the shortest if the longest burst length is set to apply the modified March tests. Results of fault coverage analysis show that the modified March test can provide 100% fault coverage of simple inter-word coupling faults.

Testing of Non-volatile Logic-Based System Chips

An non-volatile logic (NVL) -based system chip uses non-volatile storage elements to backup working state of volatile storage elements in sleep mode such that the power of chip can be turned off and zero standby power can be achieved. Since an NVL-based system chip consists of logic circuits and non-volatile storage elements, tests for logic circuits only and for non-volatile memories only are not sufficient for the testing of NVL-based system chips. The interface circuit between the volatile storage element and the non-volatile storage element must be tested as well. This paper presents possible faults occurred in the NVL-based system chips when the backup and restore operations are executed. Then, an effective test method with alternating 0/1 test sequence for detecting the defined backup and restore faults is proposed. In comparison with a straightforward test method, the proposed test method can achieve 41% test time reduction for an NVL-based design with 2537 flip flops.