Yonghong Gao

A new VLSI-oriented FFT algorithm and implementation

In this paper, we present a new VLSI-oriented fast Fourier transform (FFT) algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. This algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, an 8 K FFT ASIC is designed for use in the DVB (Digital Video Broadcasting) application in 0.6 /spl mu/m-3.3 V triple-metal CMOS process.

A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters

This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 μm 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.

A fifth-order comb decimation filter for multi-standard transceiver applications

In multi-standard transceivers programmable decimation filters are required to perform channel select filtering at baseband since the channel bandwidths, sampling rates, and CNR requirements are different. This paper presents a low power fifth-order comb decimation filter with programmable decimation ratios (16 and 8) and sampling rates (12.8 MHz and 44.8 MHz) for GSM and DECT applications. The non-recursive architecture is employed for the comb filter and low power VLSI implementation techniques are developed.

A partial-polyphase VLSI architecture for very high speed CIC decimation filters

A partial-polyphase architecture for CIC (Cascaded Integrator-Comb) decimation filters is proposed in this paper. Based on the partial-polyphase decomposition and parallel processing techniques, filters with the new proposed architecture can operate at much lower sampling rate and still achieve the same performance as Hogenauers CIC filters. With the partial-polyphase decomposition, complicated polyphase decompositions are avoided in the case of decimation ratio and filter order is high. The new architecture has advantages in high speed operation, low power consumption and low complexity for VLSI implementation. Design issues such as polyphase components, internal word length, built-in self-test scheme and layout design considerations have been discussed.

Design of a super-pipelined Viterbi decoder

This paper presents a novel super-pipelined VLSI architecture for Viterbi decoders. This architecture is capable of achieving high throughput in an area-efficient manner and hence it is an attractive architecture for implementing the Viterbi decoder where a large constraint length and high throughput rate are required. The throughput can be linearly increased by increasing the number of basic process elements. The notable advantage is its regularity and flexibility. A Viterbi decode (R=1/2 K=10) is designed in 0.6 /spl mu/m 3.3 V CMOS process to demonstrate the favourable performance of this new architecture.

Efficient VLSI implementation of radix-8 FFT algorithm

High-radix Cooley-Turkey FFT algorithms have obvious advantages: less multiplications and reduced memory accesses so power consumption can be reduced. However, the disadvantages are that traditional direct mapping implementation of high-radix butterfly element will required more complex multipliers and thus large silicon area will be consumed. In this paper, we proposed an efficient approach to realize the high radix butterfly process element. This approach employed pipelining techniques to cascade the paralleled multipliers and thus fewer complex multipliers are utilized to realize the radix-r butterfly element. This approach can achieve a good trade-off between speed and area in the design of high radix butterfly element.

Implementation of a low power 128-point FFT

In this paper a low power 128 point fast Fourier transform (FFT) processor is implemented based on our new VLSI-oriented FFT algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. A new management of the on-chip memory further reduce its power consumption. This FFT processor has been designed in 0.6 /spl mu/m 3.3 V triple-metal CMOS process with an area of 10 mm/sup 2/. The chip is capable of computing a 128 point FFT every 3 /spl mu/s and the power dissipation is 400 mW at 50 MHz input frequency.

An improved architecture and implementation of cascaded integrator-comb decimation filters

In this paper an improved version of the nonrecursive carry-save-adder-based structure for CIC (cascaded-integrator-comb) decimation filters is proposed for high speed applications. By employing parallel processing techniques, the improved structure can further increase the sampling rate of CIC filters. Low-complexity implementation of the parallel stages is also discussed.

Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems

Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

A 71 Msample/sec fifth order sigma-delta digital modulator

A 71 Msample/sec fifth order digital modulator with an oversampling ratio of 32 has been designed in a 0.6 /spl mu/m 3.3 V CMOS technology. To achieve such a high sampling rate, the structure of the modulator is carefully selected in order to reduce the latency in feedback loops. Carry-save adders are also utilized to facilitate high speed operation. Based on the analysis and simulation results, simple feedback coefficients for adjusting the NTF zero positions are employed and the internal word-length is scaled down without significant degradation of the performance.