Yoshiaki Kamigaki

Analysis of Carrier Traps in Silicon Nitride Film with Discharge Current Transient Spectroscopy, Photoluminescence, and Electron Spin Resonance

Electrical characteristics and an origin of traps in silicon nitride film were investigated using discharge current transient spectroscopy (DCTS), electron spin resonance (ESR), and photoluminescence (PL). It was found from DCTS that the density of traps of 1.1 eV from the conduction band edge increased with the increase of the gas-mixture ratio of SiH2Cl2 over NH3 for the fabrication of silicon nitride film. The energy levels of traps in silicon nitride film of 0.25, 0.68, 0.83–0.91, and 1.25–1.3 eV from the conduction band edge were found from photoluminescence observation. The ESR signals of the K-center that indicated a silicon dangling-bond increased with the increase of the gas-mixture ratio of SiH2Cl2 over NH3. It is suggested that the origin of traps of 1.1 eV from the conduction band in silicon nitride film is the silicon dangling-bond.

UV/EB Cure Mechanism for Porous PECVD/SOD Low-k SiCOH Materials

The mechanism of UV and EB cure processes for porous low-k SiCOH materials was investigated by using experimental results obtained using PECVD and SOD films as well as simulated results. Both UV and EB cures induced dielectric constant change and Youngs modulus improvement because Si-OH elimination (moisture removal) and cross-link formation occurred during film shrinkage. Excess UV curing, however, caused defects in the porous SiCOH film, as indicated by ESR analysis. The mechanism discussed in this work is applicable to most UV/EB cure systems and PECVD/SOD SiCOH materials for 45-nm-node Cu interconnects

Improvement of Written-State Retentivity by Scaling Down MNOS Memory Devices

New MNOS retention characteristic phenomena are demonstrated. Shrunk MNOS memory devices are closely evaluated. While charge retentivity of the erased state depends only slightly on silicon nitride thickness, written-state retentivity is improved by reducing silicon nitride thickness. These new phenomena are applied to memory device design. A 1 M bit MNOS EEPROM can be designed with silicon nitride thickness 20.0 nm and programming voltage 10.7 V. These results show the MNOS memory device to be a very promising candidate for Megabit EEPROMs.

Electron Spin Resonance and Photoluminescence Study of Charge Trap Centers in Silicon Nitride Films and Fabrication of Proposed Oxide?Nitride?Oxide Sidewall 2-bit/Cell Nonvolatile Memories

We have proposed a novel oxide–nitride–oxide (ONO)-sidewall 2-bit/cell nonvolatile memory and fabricated 70-nm-node nonvolatile memory devices. For low-pressure chemical-vapor-deposition (LPCVD)-SiN films, with increasing SiH4/NH3 mixture gas ratio, we have found from ESR and PL evaluation that the paramagnetic defect density increases and some PL emission energy levels become deeper. We consider that the energy-level shift is due to the effects of trap potential overlapping, where the trap centers are generated at the excess silicon atoms in the SiN films. In this study, a SiH4/NH3 mixture gas ratio of less than 1:100 was used to suppress the potential overlapping. As a result, we have also shown that the proposed memory device has high performance and excellent scalability.

Indications for an ideal interface structure of oxynitride tunnel dielectrics

Interface characteristics with respect to nitrogen-distribution and hydrogen-diffusion behavior were evaluated for two model tunnel oxides nitrided by NO and N2O gas, respectively. Nuclear reaction analysis reveals a different resistance of the two interfaces against the approach by H, which allows us to correlate the characteristic N-distribution of the tunnel oxide with a H-diffusion barrier. From the relation between the interface structure and the electrical properties of the tunnel oxynitrides, we thus propose that the ideal interface structure of reliable tunnel oxynitride features a N-rich H-diffusion barrier layer in front of the oxynitride/Si interface.

Improving program/erase endurance by controlling the inter-poly process in flash memory

Using poly-Si gate MOS capacitors, the tunnel oxide degradation due to high electric field stress is shown to be accelerated by the oxidation of the Si/sub 3/N/sub 4/ film in inter-poly ONO films and by high-temperature annealing. Microscopic Raman spectroscopy confirms that increased tensile stress in poly-Si gates leads to tunnel oxide degradation, Therefore, using CVD-SiO/sub 2/ film as the top oxide in inter-poly ONO films or using only a CVD-SiO/sub 2/ film as the inter-poly film, and reducing the high-temperature annealing time after poly-Si gate formation, will significantly increase the program/erase endurance of flash memory.

Electron Spin Resonance Observation of Bias-Temperature Stress-Induced Interface Defects at NO/N2O-Annealed Chemical-Vapor-Deposition SiO2/(100) p-Si Substrates

Using an electron spin resonance (ESR) technique, we observed bias-temperature (BT) stress-induced interface defects at chemical-vapor-deposition (CVD) SiO2/(100) p-Si substrates annealed in either NO or N2O gas. The g-factors and peak widths detected by ESR measurements are 2.0058 and 0.35 mT, and 2.0035 and 0.40 mT for interface defects, Pb0 and Pb1 centers, respectively. Before BT stress application, the total density of ESR-active defects at the interface was determined to be 1.51×1012 cm-2 for the NO-annealed sample, which is supposed to include a large number of hydrogen (H) atoms near the interface, and 1.85×1012 cm-2 for the N2O-annealed sample, which is supposed to include a small amount of H atoms. After BT stress application, the total interface defect density increases with positive BT stress time monotonically, which is mainly caused by H desorption reaction. In contrast, in the case of negative BT stress application, the total density decreases first, and then increases, which might be caused by two reactions; the first reaction is [Si\tbondSi3→Si\tbondSi3], and the second reaction is [HSi\tbondSi3→HSi\tbondSi3→Si\tbondSi3].

New Phenomena in MNOS Retention Characteristics and Their Application to Memory Device Design for Megabit EEPROM's

An MNOS memory device design for Meg:abit EEPROM s has been developed. Shrunk MNOS devices are closely evaluated. lThile charge retentivity of the erasedstate depends slightly on SisNa thlckness, written-state retentivity is improved by reducing SigNl thickness. These new phenomena are applied to memory device desiS:n. It is shown that fM bit MNOS EEPROM can be desig:ned with SisN4 thickness 2O. O nm and proS:ranming: voltage 10. ? V. These results show the MNOS device to be a very promising: candidate for Megabit EEpROlf s.