Shinichi Minami

A novel MONOS nonvolatile memory device ensuring 10-year data retention after 10/sup 7/ erase/write cycles

A highly reliable nonvolatile memory device suitable for high-density electrically erasable and programmable read only memories (EEPROMs) is described. A metal-oxide-nitride-oxide-semiconductor (MONOS) structure whose top oxide is fabricated by chemical vapor deposition (CVD) on the nitride is proposed. This CVD oxide is densified by pyrogenic annealing and has stoichiometric SiO/sub 2/ characteristics. Its potential barrier, which prevents stored charges from decaying through the top oxide to the gate, thus becomes sharper than that of the thermally grown top oxide used in the conventional MONOS structure. For comparison between the proposed MONOS, conventional MONOS, and MNOS structures, three devices were fabricated on the same process line. The 16.7-nm nitride thickness in combination with a top oxide thickness of 4.0 nm results in a gate capacitance equivalent to that of the conventional NMOS structure with a 23.5-nm nitride thickness. Moreover, an asymmetric erase/write programming voltage has been adapted to the MONOS device operation by considering both erased-state degradation and written-state retention. At 85 degrees C, the proposed MONOS device has 10/sup 7/-cycle endurance with 10-year data retention. >

New scaling guidelines for MNOS nonvolatile memory devices

New phenomena in MNOS retention characteristics that originate from stored charge distribution are described and new scaling guidelines are indicated. The most significant phenomenon is that write-state retentivity is less dependent on the programmed depth, and is improved by reducing silicon nitride thickness. This behavior suggests that write-state charges are distributed rectangularly, while erase-state charges are distributed exponentially. The lower limit of the programming voltage is determined by write-state retentivity and not erase-state retentivity, and the write-state charge distribution depth determines the lower limit of silicon nitride thickness. The upper limit of the programming voltage is determined by erase-state retentivity after erase/write cycles. The scaling guidelines indicate that 16-Mb EEPROMs can be designed using MNOS memory devices. >

A new portrayal of electron and hole traps in amorphous silicon nitride

Trap centers in amorphous silicon nitride (a‐SiNx) have been considered to be amphoteric. We found two signals of Si3 3/4 Si0 and N3 3/4 Si0 (Si dangling bonds with an unpaired electron) by an electron‐spin‐resonance method, and estimated the hole trap density to be larger than the electron trap density by about one decade, using the nonvolatile memory devices. As a result, we propose a new portrayal in which electron/hole traps are at the interface between Si clusters and a‐SiNx bulk, and hole traps are at nitrogen vacancies in a‐SiNx bulk.

Scaling Down MNOS Nonvolatile Memory Devices

Scaling down of MNOS nonvolatile memory devices are presented. Knowledge of operating mechanisms of the electrically alterable nonvolatile memory provides guidelines for choosing the proper thickness of the gate insulating films (Si3N4 and SiO2). It is found that writing time of an MNOS device depends on the nitride thickness alone but not on the oxide thickness, while erasing time depends on the thicknesses of both films. A 10-V programmable scaled down MNOS memory device is realized by decreasing nitride thickness from 50 nm to 19.5 nm and keeping oxide thickness almost constant at about 2.1 nm. Experimental devices are shown to be highly reliable, if the Si3N4 is slightly oxidized, resulting in an MONOS structure.

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 104write/erase cycles.

Improvement of Written-State Retentivity by Scaling Down MNOS Memory Devices

New MNOS retention characteristic phenomena are demonstrated. Shrunk MNOS memory devices are closely evaluated. While charge retentivity of the erased state depends only slightly on silicon nitride thickness, written-state retentivity is improved by reducing silicon nitride thickness. These new phenomena are applied to memory device design. A 1 M bit MNOS EEPROM can be designed with silicon nitride thickness 20.0 nm and programming voltage 10.7 V. These results show the MNOS memory device to be a very promising candidate for Megabit EEPROMs.

High‐resolution transmission electron microscopy study of 1.5 nm ultrathin tunnel oxides of metal‐nitride‐oxide‐silicon nonvolatile memory devices

Metal‐nitride‐oxide‐silicon (MNOS) nonvolatile memory devices have an ultrathin tunnel oxide SiO2 layer and a signal‐charge‐stored nitride Si3N4 layer. Using high‐resolution transmission electron microscopy (TEM), the cross‐sectional structure of MNOS devices has been observed for the first time, including direct observation of tunnel SiO2. The following is revealed: (1) Tunnel SiO2 of 1.5 nm thickness is fabricated very uniformly on the surface of a Si substrate. (2) No mixing of tunnel SiO2 and Si3N4 is observed even though tunnel SiO2 is extremely thin. As a result, we can suggest that tunnel SiO2 in a MNOS device exhibits very stable morphology and stoichiometry characteristics.

n-channel Si-gate MNOS Device for High Speed EAROM

New technologies for high speed and high performance electrically alterable read-only memories are developed. The memory cell consists of an n-channel silicon gate MNOS device and a switching transistor (two devices per bit). This cell configuration and advanced processing technologies realize high speed, no read-cycle limitations, long data retention and high packing density for n-channel EAROMs when compared to conventional p-channel aluminum gate EAROMs. The features of the new MNOS transistors are investigated and capability of ten year unpowered data storage at 125°C is confirmed. Write and erase times are 100 µs and several ms at 25 V, respectively. A single 5 V 2 k-bit EAROM with complete peripheral circuits is also fabricated. The measured access time is about 100 ns, which is more than five times faster than conventional EAROMs.