Yoshimitsu Yanagawa

1-Tbyte/s 1-Gbit DRAM architecture with micro-pipelined 16-DRAM cores, 8-ns cycle array and 16-Gbit/s 3D interconnect for high throughput computing

A novel DRAM architecture with an ultra-high bandwidth is proposed for high throughput computing. The proposed architecture employs three techniques: 1) five-stage pipelined 16-DRAM cores, 2) an early bar write scheme for an 8-ns cycle array operation, and 3) a 16-Gbit/s I/O circuit on each of 32 through-silicon-via pairs/DRAM core. We conducted a circuit simulation assuming a 45-nm 1-Gbit chip and confirmed that the proposed architecture achieved a 1-Tbyte/s bandwidth with 19.5-W power consumption.

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

A new sense amplifier (SA) and relevant circuits were proposed for low-power, high-speed, and small-sized 0.5-V gigabit DRAM arrays. The SA, consisting of a low-VT NMOS preamplifier and a cross-coupled high-VT PMOS latch, achieved 46% area reduction compared to our previously proposed SA with a low-VT CMOS preamplifier. Separation of the SA and a data-line pair, and overdrive of the latch achieved a restoring time of 13.4 ns and a sensing time of 6 ns. An adaptive leakage control of the preamplifier reduced the leakage current of the SA to 2% of that without the control.

On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer

A novel two-stage reaction-control scheme with a background-cancelling circuit - for reducing data volume and analysis time of an ion-sensitive-FET (ISFET) - based DNA sequencer-is proposed. The scheme successfully reduces the background noise and renders time-consuming background analysis unnecessary. It also reduces sample-to-data time by 72% (3.6 times faster) and data volume by two orders of magnitude.

0.5-V Low-

A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventional preamplifier. By activating the proposed preamplifier temporarily during the write cycle, the writing time was 16.3 ns, which is 72% shorter than the case without activation of the proposed preamplifier, and this time is short enough to apply a DRAM array using the proposed preamplifier to 1.6-Gbit/s/pin DDR3 SDRAM. The operating current of the memory array and its peripheral circuit including the proposed preamplifier was reduced by 12% by reducing the data-line voltage from 0.8 to 0.5 V.

V _{\rm T}

A charge-integration read scheme has been developed for a solid-nanopore DNA-sequencer that determines a genome by direct and electrical measurements of tunneling current in a single-stranded DNA. Although the tunneling current varies depending on the translational and rotational movement of the DNA, the developed scheme cumulates charge at the parasitic capacitance of the nanopore device so that the base-types can be distinguished even under such noisy condition. A circuit simulation demonstrates that the scheme successfully distinguishes between each DNA base at the speed of 2.0 ms/base. The speed is roughly six orders faster than that of a conventional DNA sequencer. With another scheme which reads complementary base-pair simultaneously with two nanopores, the speed is further improved, and the human genome can be sequenced in only one day if 100 nanopore systems operate in parallel with the scheme.

CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

A novel CMOS low-VT preamplifier suitable for low-voltage and high-speed mid-point sensing was developed for gigabit DRAM. This preamplifier consists of a low-VT NMOS cross couple, a low-VT PMOS cross couple and a high-VT CMOS latch. The sensing speed of the proposed preamplifier at dataline voltage of 0.5 V is 62% higher than that of a conventional preamplifier. By activating the low-VT NMOS and PMOS cross couples temporarily during write operation, writing time is 72% shorter compared to the case with the high-VT CMOS latch only. Data-line charging current of a memory cell array with the proposed preamplifier is reduced by 26% by decreasing dataline voltage from 0.8 to 0.5V.