Tomonori Sekiguchi

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation

A DRAM-cell array with 12-F 2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.

Influence of Impurities on the Performance of Doped-Well GaInAs/InP Resonant Tunneling Diodes

The influence of well impurity doping on the performance of GaInAs/InP resonant tunneling diodes (RTDs) was investigated. For undoped diodes, the peak-to-valley (P/V) current ratio was 9.7, at 2×1017 cm-3 it was 10.8, and at 2×1018 cm-3 it was 4.0. The maximum at 2×1017 cm-3 can be explained by potential bending, and the decrease at 2×1018 cm-3 can be explained by scattering. A change in the current-voltage characteristics at a doping level of 2×1018 cm-3 can be explained by potential bending in the well. Moreover, the variation in the observed width of the resonance level can explain the change in P/V ratios.

High P/V ratio of GaInAs/InP resonant tunneling diode grown by OMVPE

Abstract This paper reports higher peak-to-valley current (P/V) ratio in GaInAs/InP resonant tunneling diode (RTD) than ever. In organomettalic vapor phase epitaxy, the P/V ratio depends strongly on the partial pressure of the group V gas. The obtained P/V ratios are 9.7 and 7.4 at 4 and 77 K, respectively. The width of the resonance level is 11 meV at 4 K.

A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-/spl mu/m cost-effective DRAM technology

A 144-Mb twin-cell-memory was fabricated using 0.11-/spl mu/m cost-effective DRAM technology. A direct-sense-amp with a three-stage sensing scheme can achieve a random access time of 4.8 ns. The source-separated restore-sense-amp enables a random cycle time of 6.0 ns. The peak bandwidth is 48 Gb/s with separate I/O and simultaneous read/write operations. High performance was also realized using W/WNx dual-gate CMOS technology with a p+ gate memory-cell-transistor.

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup

A new ternary/quaternary content-addressable memory (CAM) architecture using a one-hot-spot block code and two new schemes - for large-scale flow-table lookup has been developed. An NPU-side IP-address compression scheme enables a network processor unit (NPU) to track a CAM and its usage so that IP addresses can be efficiently stored with one-hot-spot block code. A dynamic re-configurable CODEC scheme enables the CAM to store both ternary and quaternary data. With 72-bit data width per word, this CAM, using 0.13-/spl mu/m stand-alone DRAM technology, can achieve 1.5 million entries, namely, six times more than a conventional static ternary CAM.