Yoshinao Harada

Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications

This letter presents the formation of nickel nanocrystal on HfO2 high-k dielectric and its application to the nonvolatile memory devices. The effects of the initial nickel layer thickness and annealing temperature on nickel nanocrystal formation are investigated. The n-metal-oxide-semiconductor field-effect transistor with nickel nanocrystals and HfO2 tunneling dielectrics is fabricated and its programming, data retention, and endurance properties are characterized to demonstrate its advantages for nonvolatile memory device applications.

Comparison of thermal and plasma oxidations for HfO2/Si interface

Abstract The HfO2/Si interface stability has been investigated by using a rapid thermal annealing (RTA), an inductively coupled plasma (ICP) and a reactive sputtering, as a comparison of thermal and plasma oxidations of the Hf/Si interface. Reduction in both capacitance equivalent thickness (CET) and leakage current density (Jg) was difficult to be attained by the thermal oxidation since it accompanies the crystalline HfO2 with SiO2-like interface. Advantage is found for the plasma oxidation technique to oxidize Hf metal at low temperatures remaining the HfO2 in an amorphous phase with silicate interface. Reduction in both CET and Jg was attained by the plasma oxidation and a Hf metal pre-deposition technique.

Specific structural factors influencing on reliability of CVD-HfO/sub 2/

We report on two key issues for CVD-HfO/sub 2/ gate dielectric which influence their reliability. The first is extrinsic defects, i.e. two types of extrinsic defects which lead to large electrical leakage. The other issue is interfaces inside the film, i.e. stoichiometric interfaces due to Si out-diffusion from the substrate, and interfaces defined by dielectric constant transitions formed by a diffusion mechanism of Si into HfO/sub 2/. Lower Weibull slope /spl beta/ is mainly determined by the distance from the Si substrate to the k-transition interface. Although /spl beta/ becomes smaller due to the k-transition interface, it was clarified to be improved by a single layered silicate without k-transition interface.

The metal gate MOS reliability with improved sputtering process for gate electrode

The impacts of the N/sub 2/ introduced reactive sputtering deposition of WN/sub x/ or TiN gate electrodes on the gate leakage current and the dielectric reliability of the metal gate MOS capacitors are investigated. The surface nitridation of the gate dielectric during the reactive sputtering deposition dramatically improves the gate dielectric characteristics, being comparable to those of the poly-Si gate. The activation energy of charge-to-breakdown (Q/sub bd/) of the metal gates is identical with that of the poly-Si gate under the gate injection stress. Under the substrate injection stress, however, the activation energy of the metal gates is lower than that of the poly-Si gate due to the enhanced electron trapping of the metal gates.

Impacts of strained SiO/sub 2/ on TDDB lifetime projection

We clarify the effects of the strained-SiO/sub 2/ on the time dependent dielectric breakdown (TDDB) characteristics, the activation energy of the oxide breakdown and Weibull slope (/spl beta/) for the ultra-thin gate oxide. Considerations based on the extended-Stillinger-Weber potential model show that the built-in compressive strain in SiO/sub 2/ changes the statistical distribution of the Si-O-Si angle, leading to a decrease of T/sub pd/ and a spread of the distribution. The oxide breakdown tends to occur at the Si-O-Si network with a lower bond angle (/spl sim/115/spl deg/) for the 2 nm-thick SiO/sub 2//Si system.

Role of base layer in CVD Si/sub 3/N/sub 4/ stack gate dielectrics on the process controllability and reliability in direct tunneling regime

The roles of the base layer in Si/sub 3/N/sub 4//SiON stack gate dielectrics on the dielectric reliability, MOSFET performance and process controllability are investigated. The critical SiON-base layer thickness is determined as /spl sim/1 nm from the TDDB results and the physical analysis based on X-ray photoelectron spectroscopy. The obtained thickness is considered to attribute to the nitrogen profile in the SiON base and the strained layer thickness near SiON/Si interface.