Yoshinori Muramatsu

A signal-processing CMOS image sensor using a simple analog operation

A high-density CMOS image sensor has a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel and real-time operation are achieved by using a four-transistor pixel scheme and column-parallel on-chip analog operation.

A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout

Recently, the demands to achieve both high-speed and high-quality imaging — including high A/D resolution — have increased. The new target specification is 60fps Ultra-High-Definition with 12b resolution. This imaging requires 24Gb/s, while reported CMOS image sensors have reached up to 6.5Gb/s [1–4]. This paper presents a 34.8Gb/s CMOS image sensor with high image quality, which realizes 17.7M pixels at 120fps with 12b resolution and a dynamic range of over 75dB (one of the highest image qualities, compared with data from [2]). Generally there exists a trade-off between high-speed imaging and high image quality. This is because high-speed imaging brings high power with high thermal noise, which also degrades the signal quality, and because fast data transfer may require more output pins, bringing more interference.

4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing

High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1–4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1–3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.

Non-complimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAMs

A non-complimentary rewriting scheme is proposed for open-bit-line DRAMs adopting shared-sub-sense amplifier. The scheme can theoretically cancel inter-bit-line coupling noise down to zero. In order to suppress the peak in word-line noise, a serial-data coding scheme was also developed. This scheme can reduce word-line noise to at least 50%. These two circuits were applied to an experimental 1 Gb DRAM using 0.22 /spl mu/m CMOS process technology for file applications.

Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM

A noncomplimentary rewriting scheme is proposed for open-bit-line DRAMs adopting a shared subsense amplifier. The scheme can theoretically cancel inter-bit-line coupling noise down to zero. In order to suppress the peak in unselected word line noise, a serial-data coding scheme was also developed, This scheme can reduce unselected word-line noise by at least 50%.