Susumu Kurosawa

High sensitivity and no-cross-talk pixel technology for embedded CMOS image sensor

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-/spl mu/m CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si/sub 3/N/sub 4/ film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light.

A signal-processing CMOS image sensor using a simple analog operation

A high-density CMOS image sensor has a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel and real-time operation are achieved by using a four-transistor pixel scheme and column-parallel on-chip analog operation.

A new dynamic RAM cell for VLSI memories

A high density dynamic memory cell using DMOS tecnnology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing, Since the two nDMOSFET threshold states are nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, saved by using two polysilicon layers and triple self-aligned structure, is 50-60 % of the conventional one-transistor memory cell area. The DMOS cell was successfully fabricated, and the 1.2 V threshold shift and the 7 µA current difference per 1 µ channel width were obtained for 400 Å gate oxide test cell. The complete memory operation was confirmed with a 2×2 test cell array.

A new VLSI memory cell using capacitance coupling

A new VLSI memory cell, which offers small cell area, about 6F2(where F is the feature size), internal cell gain and high alpha-particle immunity is proposed. Since it employs capacitance coupling in a write operation, it requires only one bit line and is called a Capacitance-Coupling (CC) cell. A CC cell consists of three transistors and a capacitor, which are integrated in a small area by sharing their nodes with one another. The charge is stored in a P+-type diffused layer in a shallow N-type diffused layer. The P+-layer potential controls the readout current which flows through the N-layer. Experimental test devices having a 0.7\microm deep N-layer and 0.2\microm deep P+-layer were fabricated. The complete CC cell operation was confirmed.

Comparison of fully depleted and partially depleted mode transistors for practical high-speed, low-power 0.35 /spl mu/m CMOS/SIMOX circuits

Although attractive features of fully depleted mode transistors have already been clarified, essential roles of the fully depleted mode itself in improved performance of digital circuits have not been shown clearly. In this study, we examined such parameters as the propagation delay time and power consumption of 0.35-/spl mu/m CMOS/SIMOX gates (inverter, 2-6NAND, 2-6NOR) composed of fully depleted (FD), near fully depleted (n-FD), or partially depleted (PD) mode transistors with no body-contacts, and discussed the essentially important factors for high performances of CMOS/SIMOX circuits.

A new VLSI memory cell using DMOS technology (DMOS cell)

A high-density dynamic memory cell using DMOS technology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing. Since n-DMOSFET threshold state is nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, which is made small by using two polysilicon layers and self-aligned structure, is about 50 percent of the conventional one-transistor memory cell area. An analytic model for DMOS cell readout voltage is proposed. From this model, the optimum DMOS cell structure, which gives more than 0.7-V readout voltage with 2-µm channel length, is found for 5-V power supply operation. Experimental data support this model. A 7-µA readout current per 1-µm channel width is obtained for 400-Å gate oxide test cell. The complete memory operation is confirmed with a 2 × 2 test cell array.

A 3D analysis of source/drain capacitance in SOI MOSFET for practical circuit design

It is well known that the small capacitance of the source/drain (S/D) region in MOS/SOI devices is one of the most attractive characteristics for the circuit performance improvements. In order to perform the implementation of the three-dimensional (3D) effects of the S/D capacitance into circuit simulators for more precise simulations, it is strongly required to estimate 3D dependence of the S/D capacitance on transistor layout patterns. However, such effects of the 3D coupling between the adjacent S/D regions have not been investigated in detail. In this study, we analyzed 3D effects of the S/D capacitance in MOS/SOI devices using in-house simulators, and discussed the contribution of the 3D effects on the total S/D capacitance.

Design methodology for low power, high-speed CMOS devices utilizing SOI technology

We have compared CMOS gate performances between bulk and SOI structures, using the circuit simulator SPICE with the simplest assumptions. Main results are as follows: (1) We have demonstrated that it is possible to estimate CMOS/SOI performances using the circuit simulator SPICE without any specific physical models for SOI transistors. (2) The reduction effect of the drain parasitic capacitance by the CMOS/SOI technology becomes more remarkable with a decrease in the supply voltage. (3) Just by increasing the channel width of the CMOS/SOI keeping its power consumption equal to that of the CMOS/BULK, the propagation delay time dependence on large load capacitance can be improved dramatically with higher drivability.<<ETX>>

A capacitance-coupling memory cell operating with a single power supply

A capacitance-coupling (CC) memory cell structure is proposed that operates with a single power supply and provides larger storage capacitance than the conventional CC cell. This structure uses triple polysilicon technology and a self-aligned positioning technique. To obtain single-power-supply operation, two word lines are used for reading and writing. The p-channel MOSFET and the junction FET, which are included in the memory cell and are merged in one device area, are extensively studied to estimate the capability of the cell. Experimental memory cells with 1- mu m design rule were fabricated that showed complete memory operation and sufficient 0/1 readout-current ratio, and also confirmed the estimated capability results. >

The most essential factor for high-speed, low-power 0.35 μm complementary metal-oxide-semiconductor circuits fabricated on separation-by-implanted-oxygen (SIMOX) substrates

We present experimental data concerning the propagation delay time and the power consumption of 0.35 µ m complementary metal-oxide-semiconductor (CMOS) gates (inverter, NAND, NOR) fabricated on the commercial standard high dose separation-by-implanted-oxygen (SIMOX) substrates. Each CMOS gate was composed of the fully depleted (FD) mode N- and P-type metal-oxide-semiconductor (NMOS and PMOS) transistors or the partially depleted (PD) mode ones with no body-contact. On the basis of the experimental data, together with SPICE simulation results, we show that the FD-mode is not the primary factor for high-speed, low-power performances of the CMOS/SIMOX circuits, but the reduced drain parasitic capacitance (both the bottom and the peripheral components) with the thin film silicon-on-insulator (SOI) structure is. Furthermore, we show the significance of the design and control of the transistor threshold voltage and/or the off-state leakage current for high-speed, low-power CMOS/SIMOX circuits.