Yoshio Matsuda

Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

SLDRAM architecture is a proposed standard for high bandwidth, high-speed packetized DRAM. Its I/O interface, SLDRAM interface, is specified for high-speed command/address and data transfers between an SLDRAM controller and SLDRAMs. The SLDRAM interface is demonstrated through a setup involving an experimental chip and an emulation motherboard mounting several SLDRAM emulation modules. The experimental chip is packaged and mounted on a conventional PCB module. The interface of the chip operates up to 600 Mb/s per pin with a 300 MHz clock.

The maximum operating region in SiGe HBTs for RF power amplifiers

Microwave waveforms of SiGe HBTs have been directly measured. The maximum operating region has been experimentally investigated by sweeping the load lines and power of the input signal. The device is found to operate beyond the conventional BVceo, while GaAs HBTs cannot survive at that voltage. The conventional BVceo is found to limit the average Vc of the maximum load lines, but has no influence on the peak voltage. Another BVceo measured with a voltage generator is proposed to represent the avalanche breakdown instead of the conventional one.

Improvement of DC and RF Characteristics of AlGaN/GaN High Electron Mobility Transistors by Thermally Annealed Ni/Pt/Au Schottky Gate

A thermally annealed Ni/Pt/Au metal structure was employed as the gate contacts of AlGaN/GaN high electron mobility transistors (HEMTs), and their DC and RF performances were investigated. This gate structure markedly improved the Schottky characteristics such as the Schottky barrier height and leakage current. Regarding the DC characteristics, the maximum drain current and off-state breakdown voltage were increased from 0.78 A/mm (Vg=1 V) to 0.90 A/mm (Vg=3 V) due to the improved applicability of the gate voltage and from 108 V to 178 V, respectively, by annealing the gate metals. In addition, a reduction of the transconductance was not observed. Furthermore, even after the deposition of SiNx passivation film, the off-state breakdown voltage remained at a relatively high value of 120 V. Regarding the RF characteristics, the cut-off frequency and maximum oscillation frequency were also improved from 10.3 GHz to 13.5 GHz and from 27.5 GHz to 35.1 GHz, respectively, by annealing the gate metals whose gate length was 1 µm.

A C-band AlGaN/GaN HEMT with Cat-CVD SiN passivation developed for an over 100 W operation

We applied a Cat-CVD (catalytic chemical vapor deposition) passivation film to AlGaN/GaN HEMTs, to resolve the trade-off between their drain current transient time and gate-drain break down voltage. We did not employ any field plate because it degrades high frequency operation over C-band. The SiN passivation film, deposited after a NH 3 treatment, resulted in less transient time and less gate leakage current than conventional PE-CVD passivation. A T-shaped gate HEMT fabricated by this technique, with Lg = 0.4 μm and Wg = 50.4 mm, delivered an output power over 140 W (2.79 W/mm), which was a record power at C-band.

A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

Recent high-speed DRAMs adopt the architecture known as DDR (Double Data Rate) in which data are sent out at both rising and falling edges of the system clock. In order to capture the incoming data, the 90-degree phase shifter is used to shift the phase of the system clock to the center of the data period. Conventional 90-degree shifters have been organized from the PLL. In this paper, the 90-degree phase shift is achieved without a PLL. This shifter is also able to reduce the influence of the clock duty error.

A circuit design of intelligent CDRAM with automatic write back capability

The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write through

A 4-Mbit DRAM with folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell

A 5-V 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b dynamic RAM with a static column model and fast page mode has been built in a 0.8-/spl mu/m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10.9 /spl mu/m/SUP 2/ and requires only a 2-/spl mu/m trench to obtain a storage capacitor of 50 fF with 10-nm SiO/SUB 2/ equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C/SUB B/-to-C/SUB S/ capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300-mil dual-in-line package with performances of 90-ns RAS access time and 30-ns column address access time.

An 8*8 ATM switch LSI with shared multi-buffer architecture

An ATM switch LSI with a shared multibuffer architecture is proposed. With this architecture, a fourfold speed improvement is achieved in accessing buffer memories as compared to conventional shared-buffer-type switches, and high buffer memory utilization efficiency is also realized. This switch LSI is designed to operate at 100 MHz, using 0.8- mu m BiCMOS technology. Eight switch LSIs at 78-MHz operation construct a 622-Mb/s 8*8 ATM switching system with a buffer size of 8*128 ATM cells.<<ETX>>

A high reliability GaN HEMT with SiN passivation by Cat-CVD

This is the first report of catalytic vapor deposition (Cat-CVD) passivated AlGaN/GaN HEMT. We have found out that the Cat-CVD passivation film with NH3 treatment greatly enhances the reliability of the AlGaN/GaN HEMT. It is rationalized, through the low frequency capacitance-voltage measurement, that the NH3 treatment in the Cat-CVD reactor before the SiN film deposition minimizes the damage at the SiN/AlGaN interface, leading to reducing the surface trap density. The AlGaN/GaN HEMT passivated by the Cat-CVD SiN film suppresses the degradation of an output power to less than 0.4 dB under the RF operation of Vd = 30 V, f = 5 GHz after 200 h.

A Ka-band direct oscillation HBT VCO MMIC with a parallel negative resistor circuit

This paper describes a low phase noise Ka-band VCO MMIC employing InGaP/GaAs HBT processes. The VCO has the following two features: a novel circuit comprising negative resistors arranged in parallel that achieves a steep phase slope, and a tuning circuit with two resonators that offers a wide tuning range and steep phase slope. Measurement results of the developed VCO show a phase noise ranging from -111 to -114 dBc/Hz at an offset frequency of 1 MHz, and a tuning bandwidth above 1.1 GHz in a 38-39 GHz band.