Youchul Jeong

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach

Hybrid analytical modeling method for split power bus in multilayered package

As multiple chips are being integrated into a single package with increased operating frequency, switching noise coupling on power buses has become an important design issue. To reduce the noise coupling, a split power bus structure has been generally used in package substrates having multilayered power and ground planes. Consequently, there is an increasing need for an efficient method to analyze a split power bus in a multilayered package. This paper introduces a hybrid analytical modeling method for characterizing a split power bus in a multilayered package. The proposed method uses a resonant cavity model combined with a segmentation method. Furthermore, a port assignment technique and an associated calculation method for the equivalent circuit model parameter of the split gap are proposed. The proposed port assignment technique and the analytical equation make it possible to analyze a split power bus, especially in a multilayered package. To verify the proposed method, multilayered test packages are fabricated and tested by means of frequency-domain measurements. In addition, an optimal power bus design method was successfully demonstrated for suppressing noise coupling between chips on a single package. Finally, the proposed method and optimal power bus design method was verified using a series of frequency-domain and time-domain measurements

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz.

Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor

Significant reduction of power/ground inductive impedance and SSN suppression was successfully demonstrated by using embedded capacitor film in high performance package and PCB up to 3GHz frequency range. The reduction of the inductance impedance and SSN are acquired by the help of reduced via inductance in the embedded film capacitor.

High dielectric constant thin film embedded capacitor for suppression of simultaneous switching noise and radiated emission

We have thoroughly investigated and experimentally demonstrated the great advantages of thin film embedded capacitors of high dielectric constant in reducing power/ground impedance and suppressing SSN and radiated emission up to a frequency of 1 GHz. About 10 dB or more suppression of the radiated emission was acquired for a wide frequency range, including high-numbered harmonics of the clock frequency, by using the thin film embedded capacitor of high dielectric constant.

Noise coupling to signal trace and via from power/ground simultaneous switching noise in high speed double data rates memory module

We suggested the model to demonstrate simultaneous switching noise (SSN) coupling to signal and verified experimentally. There are two coupling mechanisms; one is the SSN coupling through the reference changing via, and the other is the SSN coupling through the signal trace. Through measurement and analysis, we confirmed that the worst SSN coupling occurs when strip lines have the signal via changing reference plane with SSN. Furthermore, we demonstrated that the power/ground noise coupling to the signal is reduced by placing the reference changing via at the position where the power/ground cavity impedance is low, or by adjusting the line length between two reference changing vias.

Hybrid analytical modeling of noise coupling to signal traces in a power bus with embedded film capacitor

An accurate hybrid analytical method is proposed to determine the coupling of switching noise to signal traces in a multilayer power bus with embedded film capacitor. We used the induction equivalent theorem to derive the solution of noise coupling and the segmentation method to calculate the electric field of the noise in a power bus. The proposed method was verified by measurements of impedance parameters in the frequency domain

Matrix substitution method for power bus analysis with isolated power island in high-speed packages and PCBs

We propose a matrix substitution method for analyzing a power bus containing a power island in high-speed packages and printed circuit boards (PCBs). The method is based on a segmentation method and a resonant cavity model for a rectangular cavity, and the impedance of the power bus containing the power island can be calculated analytically. Finally, the proposed method is verified by means of impedance measurements in the frequency domain

Slot Transmission Line Model of Interconnections Crossing Split Power/Ground Plane on High-speed Multi-layer Board

In the design of high-speed multi-layer board, the partitioning of the power/ground plane breaks return path of the signal current through either power plane or ground plane, which causes unwanted side effects such as reflection, crosstalk and radiation. In this paper, we have analyzed the effects of split power/ground plane on signal integrity experimentally and numerically. We have proposed equivalent circuit model of the signal traces crossing the ground slot, based on slot transmission line model. The reflection, transmission and crosstalk waveforms can be simulated and explained rigorously using the proposed model, regardless of the type of slot end.

Radiated emission from plasma display panel (PDP) depending on addressing line structure and current driving scheme

Plasma Display Panel (PDP) is a significant source of EM noise due to 11s large panel size and enormous amount of . -driving current. In this paper, we investigated the eflec!. of the addressing 1ine.structure on the panel, .and the current . driving scheme on the radiated emission from the PDP. Firstly, we have demonstrated that the address operation is the main source of the radiated emission in a frequency range‘j?om 30MHz.to 200hHz. And we also showed that -the radiated emission from the dual addressing rype is .lower ihan that of the single addressing type by about IOdB.