Hyunjeong Park

Hybrid analytical modeling method for split power bus in multilayered package

As multiple chips are being integrated into a single package with increased operating frequency, switching noise coupling on power buses has become an important design issue. To reduce the noise coupling, a split power bus structure has been generally used in package substrates having multilayered power and ground planes. Consequently, there is an increasing need for an efficient method to analyze a split power bus in a multilayered package. This paper introduces a hybrid analytical modeling method for characterizing a split power bus in a multilayered package. The proposed method uses a resonant cavity model combined with a segmentation method. Furthermore, a port assignment technique and an associated calculation method for the equivalent circuit model parameter of the split gap are proposed. The proposed port assignment technique and the analytical equation make it possible to analyze a split power bus, especially in a multilayered package. To verify the proposed method, multilayered test packages are fabricated and tested by means of frequency-domain measurements. In addition, an optimal power bus design method was successfully demonstrated for suppressing noise coupling between chips on a single package. Finally, the proposed method and optimal power bus design method was verified using a series of frequency-domain and time-domain measurements

High dielectric constant thin film embedded capacitor for suppression of simultaneous switching noise and radiated emission

We have thoroughly investigated and experimentally demonstrated the great advantages of thin film embedded capacitors of high dielectric constant in reducing power/ground impedance and suppressing SSN and radiated emission up to a frequency of 1 GHz. About 10 dB or more suppression of the radiated emission was acquired for a wide frequency range, including high-numbered harmonics of the clock frequency, by using the thin film embedded capacitor of high dielectric constant.

Antimicrobial resistance patterns (1999-2002) and characterization of ciprofloxacin-resistant Neisseria gonorrhoeae in Korea.

Background: Antimicrobial susceptibilities of Neisseria gonorrhoeae were monitored during 4 years. In Korea, ciprofloxacin-resistant N. gonorrhoeae has dramatically increased after recommendation as a therapeutic drug. Goal: The goal of this study was to determine the resistance patterns and characterize Korean ciprofloxacin-resistant N. gonorrhoeae. Study Design: Antimicrobial susceptibilities were performed. PFGE profile and DNA sequencing of gyrA and parC genes were used to characterize the ciprofloxacin-resistant isolates in Korea. Results: Tetracycline, ofloxacin, ciprofloxacin-resistant isolates were increased and among them, the proportion of isolates resistant to ciprofloxacin increased remarkably from 1% in 1999 to 48.8% in 2002. Fifteen different types by PFGE profile were identified. Major alteration type was M12 (67%), which have amino acid substitution in gyrA (S-91→F, D-95→G) and parC (S-87→A). Conclusion: We could conclude that resistance for ciprofloxacin was remarkably increased during 4 years. Ciprofloxacin-resistant N. gonorrhoeae was supposed by the spread of several strains that had a small number of origins.

Co-Modeling and Co-Simulation of Package and On-Chip Decoupling Capacitor for Resonant Free Power/Ground Network Design

The co-modeling and co-simulation results about the package and on-chip power/ground network have been demonstrated. The inevitable parallel resonance peak, due to the inductive parasitic on the package and on-chip decoupling capacitor, was analyzed in frequency domain. Subsequently, the co-design procedure for the resonant free power/ground network was suggested and evaluated simply in frequency domain.

Design of a Low-Noise UWB Transceiver SiP

Ultrawideband (UWB) wireless communication systems are emerging as a promising solution for high-data-rate and short-distance wireless data transmission. In this article, we introduce a low-noise UWB transceiver SiP design for a compact implementation in a small mobile platform. The SiPs transmitter chip has a fully digital circuit implementation with a passive band-pass filter to meet a US Federal Communications Commission (FCC) regulation, and the receiver chip has a noncoherent architecture. To reduce noise generation and coupling in the densely integrated design, we considered signal integrity issues in the high-frequency channel and power integrity issues on the power distribution network (PDN) in the SiP substrate. Circuit-level and full-wave simulations confirm that the proposed design methodology improves signal integrity and power integrity. The UWB transceiver SiP consists of a fully digital transmitter system and a noncoherent receiver system.

Modeling and simulation of IC and package power/ground network

The modeling and simulation results about the IC and package power/ground network have been depicted. With the modeling for broadband frequency region, the effect of each part in power/ground network on IC and package was analyzed in frequency domain. Keywords-modeling; simulation; power/ground network; high frequency; IC and package

Power/ground noise immunity test in wireless and high-speed UWB communication system

This paper presents a wireless and high-speed transceiver system for Ultra-Wideband (UWB) communication with a high noise immunity. A proposed transceiver system has a high-speed data transmission up to 130 Mbps. Then, the measurement setup for the noise immunity test is introduced. Also, in order to demonstrate a noise immunity of the system, timing jitter, accumulated waveform, and bit error rate (BER) are measured in the presence of a power/ground noise with various frequencies or amplitudes. The numerous measurement results help to understand the relationship between the power/ground noise and the noise immunity of the proposed transceiver system.

Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network

In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1MHz to 3GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN.

Design of UWB Transceiver SiP for Short Range Communication

Since UWB system uses a wide frequency range from 3.1 GHz to 5.1 GHz, package parasitic effects have been a hot issue which affects system malfunction. To prevent such malfunction, SiP technology is adjusted considering not only a circuit performance but various design issues in a package from viewpoints of signal integrity and power integrity. Furthermore, UWB band-pass filter is embedded into a package to reduce a complexity of transmitter circuit and the power consumption. Designed UWB SiP performance is verified by the measurement in time domain.

Frequency behavior of embedded epoxy/SrTiO 3 composite capacitor materials

Epoxy/BaTiO3 composites have been of great interest as embedded capacitor materials, mainly due to high dielectric constant of ceramic powders, and good process compatibility of epoxy with printed circuit boards (PCBs). However, one of the potential problems of epoxy/BaTiO3 composite is the dielectric relaxation at GHz range. In this paper, epoxy/SrTiO3 composite ECFs were fabricated for high frequency applications. Dielectric constants of epoxy/SrTiO3 composite embedded capacitor films with various SrTiO3 particles loading for three different commercial SrTiO 3 powders were measured from 100 Hz to 1 MHz, and experimental data at 100 kHz were fitted to the Lichtenecker equation for the prediction of the effective dielectric constant of SrTiO3 powders in epoxy/SrTiO3 composite ECFs. Using a rectangular cavity resonator method, dielectric constants of epoxy/SrTiO 3 composite ECFs were measured at GHz range (1-10 GHz). At GHz frequencies, dielectric constants of epoxy/SrTiO3 composite ECFs were nearly constant. In contrast, epoxy/BaTiO3 composite ECFs showed significant decrease of dielectric constants above 5GHz. Therefore, it is concluded that epoxy/SrTiO3 composite ECFs cab be more effectively to be applied for high frequency applications.