Younghoon Hyun

The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.

Evaluation of Seebeck coefficients in n- and p-type silicon nanowires fabricated by complementary metal?oxide?semiconductor technology

Silicon-based thermoelectric nanowires were fabricated by using complementary metal-oxide-semiconductor (CMOS) technology. 50 nm width n- and p-type silicon nanowires (SiNWs) were manufactured using a conventional photolithography method on 8 inch silicon wafer. For the evaluation of the Seebeck coefficients of the silicon nanowires, heater and temperature sensor embedded test patterns were fabricated. Moreover, for the elimination of electrical and thermal contact resistance issues, the SiNWs, heater and temperature sensors were fabricated monolithically using a CMOS process. For validation of the temperature measurement by an electrical method, scanning thermal microscopy analysis was carried out. The highest Seebeck coefficients were - 169.97 μV K(-1) and 152.82 μV K(-1) and the highest power factors were 2.77 mW m(-1) K(-2) and 0.65 mW m(-1) K(-2) for n- and p-type SiNWs, respectively, in the temperature range from 200 to 300 K. The larger power factor value for n-type SiNW was due to the higher electrical conductivity. The total Seebeck coefficient and total power factor for the n- and p-leg unit device were 157.66 μV K(-1) and 9.30 mW m(-1) K(-2) at 300 K, respectively.

High performance platinum-silicided p-type Schottky barrier metal-oxide-semiconductor field-effect transistors scaled down to 30 nm

Platinum-silicided p-type Schottky barrier metal-oxide-semiconductor field-effect-transistors with sizes varying from 350 to 30 nm were fabricated on silicon-on-insulator substrates. Threshold voltage, subthreshold swing, drain-induced barrier lowering, and saturation current were investigated as a function of gate length and channel width. The device with a gate length of 30 nm showed excellent short channel characteristics with an on/off current ratio larger than 107, an off-leakage current less than 10 pA/μm, and a subthreshold swing of 110 mV/decades.

Temperature distribution analysis of silicon nanowire for thermoelectric applications

Silicon has been considered as an impropriate material for the thermoelectric applications due to its high thermal conductivity. Recently, it has been reported that even though bulk silicon is a poor thermoelectric material, nanostructured silicon has the possibility to be a good one due to the strong suppression of phonon propagation. In our study, test structures were devised and fabricated for the characterization of thermoelectricity in nanowire structured thermoelectric devices. The temperature gradient was induced by micro-heater for the evaluation of Seebeck coefficients and the temperature measurement of hot and cold sides were done by micro-temperature sensors, installed on a test structure, respectively. In addition, temperature distribution along the nanowire was measured by Scanning Thermal Microscopy and compared with simulated results.

Pre-silicidation annealing effect on platinum-silicided Schottky barrier MOSFETs

We fabricated platinum-silicided p-type Schottky barrier MOSFETs (SB-MOSFETs) with 40 nm gate length on a silicon-on-insulator wafer. In order to improve the device performance, the devices were annealed at a temperature of 900 °C in a nitrogen environment prior to the platinum deposition for source/drain silicide formation. As a result, lowered threshold voltage of 1.2 V, subthreshold swing values of 110 mV and an enhanced on/off current ratio larger than 107 were obtained. This improvement is attributed to the reduction of the fixed oxide charge in the gate oxide during the annealing process.

Schottky barrier single electron and single hole transistors

Schottky barrier single electron/hole transistor (SB-SET/SB-SHT) are manufactured using erbium-silicide and platinum-silicide as source and drain materials. In room temperature, the manufactured SB-SET and SB-SHT showed typical FET behavior with high drive current, 550 and −376 µA/µm, respectively. At 7 K, these devices showed SET and SHT characteristics. The measured coulomb gaps are about 170 mV for the SB-SET and 220 mV for the SB-SHT. From these, the estimated sizes of the islands are 12.5 and 9.1 nm, respectively. In SB-SET and SB-SHT, high transconductance can be easily achieved because silicided electrode eliminates parasitic resistance. Moreover SB-SET and SB-SHT can be operated as conventional FET and SET/SHT depending on the bias conditions, which is very promising for SET/FET and SHT/FET hybrid applications.