Yu-Wei Huang

Superconductivity and the metal-semiconductor transition in the septenary oxide system, (Tl0.5Pb0.5)(Ca1−yYy)Sr2Cu2O7−δ

Abstract The septenary compound (Tl0.5Pb0.5)(Ca1−yYy)Sr2Cu2O7−δ exhibits the highest superconducting transition temperature (110 K) yet observed in the TlCaBa2Cu2O7−δ (1122) structure type. This complex, six-blend combination of metallic elements which make up the material is, however, compensated by a relatively simply crystal structure, which bears many similarities to that of 90 K superconductor YBa2 Cu3O7−δ. In this note we report some important features of the cation-substitution chemistry of the title compound, drawing attention to the fundamental changes in the electronic properties of the (Tl0.5Pb0.5) (Ca1−yYy)Sr2Cu2O7−δ system as Ca2+ is replaced by Y3+. Superconductivity is observed over the homogeneity range y = 0–0.5, with the superconducting transition temperature showing a maximum (108 K) at y = 0.2. Across the homogeneity range y = 0.6–1.0, the material undergoes a metal-semiconductor transition.

Accelerated formation of 110 K high Tc phase in the Ca-and Cu-rich Bi-Pb-Sr-Ca-Cu-O system

The crystal structure and superconducting properties of the Bi‐Pb‐Sr‐Ca‐Cu‐O system with Ca‐ and Cu‐rich nominal composition were investigated. A nearly single‐phased 110 K high Tc superconductor can be obtained with 852 °C/20 h sintering from the starting composition of Bi1.7Pb0.4Sr1.6Ca2.4Cu3.6Oy. X‐ray diffraction patterns, resistivity measurement, diamagnetic susceptibility results, and scanning electron micrographs all indicate that the Ca‐ and Cu‐rich nominal composition would result in better superconducting properties than those of Ca:Sr=1:1 Bi‐Pb‐Sr‐Ca‐Cu‐O compounds in a much shorter sintering time.

Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2 at an ambient temperature of 150°C.

Epitaxial Growth of High-Tc Bi-Ca-Sr-Cu-O Superconducting Layer by LPE Process

A Bi-Ca-Sr-Cu-O epitaxy layer has been successfully synthesized by the liquid-phase epitaxial (LPE) process on the MgO(001) substrate. X-ray diffraction patterns and SEM surface morphology analysis indicated a highly preferred orientation. This film showed superconductivity with onset and zero resistivity temperature of 110 K and 81 K, respectively.

Bulk Superconductivity of the (Tl0.5Bi0.5)(Ca1-xYx)Sr2Cu2Oy System

A family of (Tl0.5Bi0.5)(Ca1-xYx)Sr2Cu2Oy compounds with x=0, 0.1, 0.2, 0.3, 0.5 and 0.7 were studied systematically. The major phase (above 90%) of all sintered samples was identified as (Tl, Pb)CaSr2Cu2Oy, an isostructure of the 1122 phase. A maximum Tczero up to 102 K was achieved at x=0.2, and semiconducting behavior was found at x=0.7. The magnetization measurement is consistent with the resistance data observed. The c-axis of a unit cell contracted significantly and monotonically as the Y substitution increased. It appears that the reduction of the interlayer distance as well as the excess positive charge introduced by substitution played an important role on superconductivity; the difference from a similar Y-substituted Bi2(Ca1-xYx)Sr2Cu2Oy system was discussed.

Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

Process, assembly and electromigration characteristics of glass interposer for 3D integration

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Development and characterization of rigid-flex interface

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays

Bulk superconductivity with Tc (zero) up to 95 K in a Tl0.5Pb0.5Ca0.9Ce0.1Sr2Cu2 oxide with an Y1Ba2Cu3Oy‐like structure

Bulk superconductivity with Tc (zero) up to 95 K in a Tl0.5Pb0.5Ca0.9Ce0.1Sr2Cu2 oxide with an Y1Ba2Cu3Oy ‐like structure was observed. Single‐phase samples, tetragonal in structure with a=0.380±0.001, c=1.195±0.001 nm, and of P4/mmm space group, were prepared. The results represent the first case where Ce substitution significantly raised the Tc of a known compound. The samples were remarkably homogeneous both in composition and structure. The compounds were highly reproducible and stable. The preparative conditions were found to be much less stringent than those of other copper‐based high Tc superconductors.