Ren-Shin Cheng

Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration

In this investigation, Cu/Sn lead-free solder microbumps with 10μm pads on 20μm pitch are designed and fabricated. The chip size is 5mm × 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (−55⇆125°C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5μm pads on 10μm pitch) lead-free solder microbumping is explored.

Reliable Microjoints Formed by Solid–Liquid Interdiffusion (SLID) Bonding Within a Chip-Stacking Architecture

In this research, thousands of 20-μm pitch microbumps with a diameter of 10 μm and a structure of a pure Sn cap on a Cu pillar were electroplated on 8-inch wafers, and those wafers were then respectively singularized as a top chip and bottom Si interposer for stacking. Two methods, namely conventional reflow and solid-liquid interdiffusion (SLID) bonding, were adopted to interconnect the microbumps. In the former case, the as-plated Sn caps were fluxed, and the chip was then placed on the Si interposer. Afterward, the Sn caps on the chip and on the Si interposer were melted and interconnected at a peak temperature of 250 °C. The flux residues were cleaned after reflow, and the microgap between the chip and the Si interposer was fully sealed by a capillary underfill. In the SLID bonding process, the oxides on the as-plated Sn caps were removed by a plasma etcher first, and then the chip was placed on the interposer with a bonder as well, subsequently, the Sn caps were heated to 260°C to react with the Cu pillar to form Cu6Sn5. In the final step, the intermetallic microjoints were protected by the same capillary underfill. After assembly, the Joint Electron Devices Engineering Council preconditioning test was used to screen the test vehicles for reliability assessment, and then a temperature cycling test was performed to predict the lifespan of the microjoints. The test results showed that the microjoints formed by SLID bonding provided a superior reliability performance to those assembled by reflow. The fracture of the microjoints was caused by the volume contraction induced by the growth of Cu6Sn5, but the failure mechanisms of those two microjoints were quite different.

Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

Investigation of the process for glass interposer

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60цm-pitch solder micro bump interconnections

Three dimensional integration circuits technology has received much attention recently since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have been widely used and thermocompression bonding process are well adopted to form the connection between bumps. However, the prefect joint contour is difficult to obtain and control by such kind of bonding process in solder micro bump joints. For fine-pitch solder micro bump interconnections, the effect of joint shape on the reliability performances of the solder micro bump joints is not concluded yet till now and needs to be clarified. In this study, the effect of joint shape controlled by thermocompression bonding on the reliability performance of solder micro bump interconnections with a pitch of 60 um was discussed. The chip-to-chip test vehicle having more than 4000 solder micro bump interconnections with a bump pitch of 60 um was used in this study. A solder micro bump structure of Cu/SnAg having a thickness of 7 um/10 um was fabricated in both the silicon chip and substrate. To evaluate the effect of joint shape, four types of joint shape were controlled and made. The first type had a conventional shape of micro joint. Compared to the first one joint structure, the second type of joint structure showed the compressed shape. The third type of joint structure was the pillar-like micro joint while the fourth type of joint structure presented a neck shape having the highest joint height among all the joint structures tested. We used the fluxless thermocompression bonding process to form these four types of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of joint shape on the reliability properties of those four types of solder micro bump interconnections. The reliability results presented that all the types of joint structures could pass TCT of 1000 cycles and HTS of 1000 hours but high variation of daisy chain resistance more than 15% would happen in the neck-shape micro joint after TCT. For the neck-shape micro joint, the high variation of daisy chain resistance after TCT resulted from the cracking propagated along the interface of Cu UBM/Cu6Sn5 IMC and across the tin solder. The cracking situation was more serious as compared to the other three tested micro joints. The results of HTS revealed that resistance variation mainly depended on the micro structural evolution within micro joints tested. Electromigration test was conducted under the testing condition of 0.56 A/150°C. A daisy chain structure was adopted. For both the pillar-shape and neck-shape micro joints, Cu UBM consumption and formation of large void were the major microstructure evolutions within the micro interconnections during EM testing. The conpressed-shape showed the longer electromigration lifetime among all the types of micro joints tested.

Influence of surface morphology on the adhesion strength of plated Cu on the build-up layer within an embedded active package

Recently, System in Package (SiP) technology is used to integrate a number of integrated circuits (ICs) enclosed in a single package or a module, which attracts a great attention from electronic industries due to its characteristics of smaller size, higher performance, lower overall cost and reduction of time to market. Based on the configurations of current SiP, there are two types of structure: (1) 2D package, such as the multi-chip package (MCP) and (2) 3D package, such as multi-chip package (MCP), stacked dies, package on package (PoP) and package in package (PiP). Although 3D interconnection by through silicon via (TSV) is beneficial to enhance the transmission of signal between ICs, but the processes are costly and are not stable enough for mass production. ITRI has developed a novel PoP structure mutated from the announced embedded active technology by semi-additive process (SAP). The purpose of this study was to enhance the reliability of the PoP by establishing an optimal process window of the chemical processes used. For achieving this, 2 pieces of 40 μm thick Ajinomoto build-up film (ABF, GX-13R) were laminated to embed a 50 um thick chip in a carrier substrate, in order to improve the adhesive strength of Cu on the ABF, different processing factors such as the pressure profiles of lamination, curing conditions, and desmear parameters were used to form various surface morphologies of the ABF, the relationships between the morphologies and the adhesion strengths were learned by a peeling test. As the experiment results showed, the adhesion strength of Cu on ABF was more significantly influenced by the surface morphology of ABF, rather than the surface roughness, and a coral morphology was believed to greatly improve the adhesion strength than the needle and plated ones.

Development of high throughput adhesive bonding scheme by wafer-level underfill for 3D die-to-interposer stacking with 30µm-pitch micro interconnections

In 3D integration, die stacking together with underfilling by capillary-type underfill are the principal processes within whole conventional assembly process. How to integrate and shorten the total process steps during assembly and increase the die-stacking yield especially for thin die stack to improve the throughput that can meet the requirement from industry will be a crucial issue. In this investigation, we proposed the high throughput adhesive bonding scheme by using wafer-level underfill material for the die-to-interposer stacking with 30μm-pitch micro interconnections. The reliability characterization of the die-to-interposer stack by such bonding scheme was implemented and confirmed. Die-to-interposer test vehicle was adopted to develop the proposed adhesive bonding scheme. The micro joints of electroplating Cu/Sn solder micro bumps joined with electroplating Cu/Ni/Au micro bumps was selected as the joining structure. There were more than 3000 bumps designed in the test vehicle. Three types of wafer-level underfill material were evaluated and selected to be the suitable processing material. The optimized die-to-interposer boding profile by wafer-level underfill were developed and determined for the purpose of high throughput in this study. After assembly process by the developed adhesive bonding scheme, reliability characterization was conducted on the die-to-interposer modules. Pre-conditioning, temperature cycling test (TCT), thermal & humidity storage test (THST) and die shear test were selected to assess reliability performance of the die-to-interposer module assembled by the proposed adhesive bonding scheme. Under the optimized bonding profile, one-die assembly could be finished less than 20 seconds, which was comparable to the process time of thermocompression bonding only. Also, the wetting and joining abilities of the micro joints were as good as those bonded by thermocompression bonding with flux and no voids were found between dies. By such adhesive bonding scheme, processes of flux cleaning and underfill dispensing and curing were no longer necessary, which could apparently enhance the throughput of die stacking. Results of reliability tests revealed that no electrical-connectivity fail and delamination happened on those die-to-interposer modules with 30μm-pitch micro interconnects after TCT of 1000 cycles and THST of 1000 hours though die shear strength showed a slight degradation less than 20%. In this investigation, the developed high throughput adhesive bonding scheme displayed the high potential that could be suitable and applicable for fine pitch 3D integration and high volume manufacturing requirements.

Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology

Abstract With the current high demand for energy saving and low power consumption, numerous studies have been conducted to meet this requirement. Higher switch efficiency is one of the factors for power saving in power inverters and converters. Among the methods for improved switch efficiency, the modified package structure is one of the solutions. An embedded power module enables shortened transmitting routes and lower parasitic reactions, suggesting better power switching performance. Meanwhile, embedding allows the power devices to integrate active or passive devices above or beneath a component, leading to a three-dimensional packaging structure. This feature is also applicable in the integration of power devices because of its double side contact structure. Four dies that contain two insulated gate bipolar transistors and two diodes in this study were embedded and integrated in a carrier substrate to produce a next-generation power inverter module. The process began by attaching a die on a Cu lead frame by a SAC305 solder paste. This is followed by a lamination process to form a built-up dielectric layer on the Cu lead frame. The conducting vias and circuits were formed on the built-up dielectric layer by a UV laser and were metalized with sputtered seed layer and electroplating. The circuit layout can be revealed with subsequent etching processes by hatching another layer of electroplated Sn using UV laser. Finally, a layer of solder mask was printed to prevent electric shock on the surface layer. Structure and process features are discussed, and electrical testing and reliability tests are conducted in this paper.