Tai-Hong Chen

Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking

In this study, we used a chip-on-chip test vehicle with 30μm pitch lead-free solder micro bump to study the electromigration reliability of solder micro bump interconnection used for 3D chip stacking. The structure of micro bump composed of Sn2.5Ag solder material with Cu/Ni under bump metallization (UBM) was selected. Two types of interconnection were chosen to evaluate the effect of the joint structure on electromigration behavior. The type I was the chip stacking sample with the IMC / Sn (5 um thick) / IMC joint structure, while the type II was the sample with fully transformed Ni3Sn4 intermetallic (IMC) joints made by the post-treatment of long time thermal aging. Electromigration test was performed on the four point Kelvin structure and daisy-chain structure under the current stressing of 104∼105 A/cm2 at an ambient temperature of 150°C. During the electromigration test, the resistance increase was in-situ monitored to determine the definite time to failure. The microstructure evolution was also examined at different stages of joint resistance increase. From the testing results, the rapid increase of joint resistance was found at the early stage under current stressing in the type I micro bump. After that, the joint resistance increase became slower. This mild increasing stage was much longer than the early stage. For the type II sample, however, the resistance increasing rate was quiet lower than that of the type I sample at the identical testing time. With a higher current density in the order of 105 A/cm2 in the micro joint, the effect of joule heating caused the damage happened in Al trace and Cu UBM while the residual Sn solder had been transformed to be Ni3Sn4 IMC totally and few voids were found around IMC by the microstructure observation. When applied a current density in the order of 104 A/cm2 on the micro joint, the residual Sn was also fully transformed to be IMC. However, the failure mode of the micro joint is not clear yet because the experiments are still on-going. The resistance variation is showing a steady state under such a condition of current stressing and so far no open failure happened.

Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2 at an ambient temperature of 150°C.

Effects of Bonding Parameters on the Reliability of Fine-Pitch Cu/Ni/SnAg Micro-Bump Chip-to-Chip Interconnection for Three-Dimensional Chip Stacking

As the demands for portable electronic products increase, through-silicon-via (TSV)-based three-dimensional integrated-circuit (3-D IC) integration is becoming increasingly important. Micro-bump-bonded interconnection is one approach that has great potential to meet this requirement. In this paper, a 30-μm pitch chip-to-chip (C2C) interconnection with Cu/Ni/SnAg micro bumps was assembled using the gap-controllable thermal bonding method. The bonding parameters were evaluated by considering the variation in the contact resistance after bonding. The effects of the bonding time and temperature on the IMC thickness of the fabricated C2C interconnects are also investigated to determine the correlation between its thickness and reliability performance. The reliability of the C2C interconnects with the selected underfill was studied by performing a -55°C- 125°C temperature cycling test (TCT) for 2000 cycles and a 150°C high-temperature storage (HTS) test for 2000 h. The interfaces of the failed samples in the TCT and HTS tests are then inspected by scanning electron microscopy (SEM), which is utilized to obtain cross-sectional images. To validate the experimental results, finite-element (FE) analysis is also conducted to elucidate the interconnect reliability of the C2C interconnection. Results show that consistent bonding quality and stable contact resistance of the fine-pitch C2C interconnection with the micro bumps were achieved by giving the appropriate choice of the bonding parameters, and those bonded joints can thus serve as reliable interconnects for use in 3-D chip stacking.

Development of Cu/Ni/SnAg Microbump Bonding Processes for Thin Chip-on-Chip Packages Via Wafer-Level Underfill Film

3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (μ-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <; 50 μm at the outermost region of the packaging structure without μ-bumps significantly reduces approximately 2 μm of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the structural optimization of packaging assemblies via the WLUF.

Development of a Novel Compliant-Bump Structure for ACA-Bonded Chip-on-Flex (COF) Interconnects With Ultra-Fine Pitch

The demand for high-density electronic applications is growing. This work develops a novel chip-on-flex (COF) package with sidewall-insulated Au-coated polyimide (PI) compliant-bumps. A double-layer anisotropic conductive adhesive (ACA) material that meets the assembly requirement is adopted for the ultra-fine pitch interconnects. A process for manufacturing 20- μm pitch compliant-bumps is proposed for ACA-bonded COF packages. The double-layer ACA consists of an ACA layer with a diameter of 2.8 μm conductive particles and an NCA layer as an interlayer to bind a silicon chip with a flexible substrate. The bonding accuracy for ultra-fine pitch is determined using X-rays. To evaluate the quality of bonding, the electrical insulation is tested and the contact resistance of the daisy chain with 606 input/output (I/O) around the periphery of the chip is measured. The double-layer ACA material is assembled at different bonding temperatures to study the effects of bonding temperature on the interface adhesion using differential scanning calorimetry (DSC) and a 90° peeling test. The reliability of the fabricated COF interconnects is also evaluated by performing an 85°C/85% relative humidity thermal humidity storage test (RH THST) for 1000 h and a -55°C ~ 125°C thermal cycling test (TCT) for 1000 cycles. The interfaces between the silicon chip and the substrate of the failed samples in the reliability tests are then observed using the cross-sectional scanning electron microscopy (SEM). The compliant-bump-bonded samples with the double-layer ACA provide their excellent electrical insulation performance even at a joint space of 5 μm whereas the Au-bump samples have a short-circuiting rate of more than 50%. Notably, the contact resistance also remains stable and varies by under 3% in both the RH THST for 1000 h and the TCT for 1000 cycles. The presented results show the reliable bonding quality and stable contact resistance of the COF package that is bonded with the compliant-bump structure using the double-layer ACA, indicating its great potential for use in ultra-fine pitch applications.

Development and characterization of rigid-flex interface

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays

A novel compliant-bump structure for ACA-bonded chip-on-flex (COF) interconnects with ultra-fine pitch

As the growing demand for high-density electronic applications, a novel COF package with sidewall-insulated Au-coated polyimide (PI) compliant-bumps using a double-layer ACA that can meet the assembly requirement is thus developed for ultra-fine pitch interconnects in this work.

3D Stacking DRAM using TSV technology and microbump interconnect

As CPU performance has continually enhanced by transistor scaling, the demand in DRAM performance has been also increased. To meet the performance requirement, 3D chip stacking using Through-Silicon-Via (TSV) has been developed in recent years. For TSV technology, devices are connected by short vertical through-wafer via and thus enhance the performance such as high density, low power and high bandwidth. As transistor scaling becomes more difficult, TSV offer the promising solution for further performance enhancement. TSV formation, wafer thinning, microbump fabrication and chip stacking are key processes for 3D chip stacking using TSV. In this paper, the process steps of TSV formation are examined and discussed. On the other hand, since chip strength of thinned wafer is significantly decreased, the impact of wafer thinning on DRAM devices performance is also presented. After TSV formation, the fine pitch microbumps are fabricated for chip connection. At last, the 5-strata C2W stacking using Cu filled TSV and Sn-Ag/Cu microbump is achieved

Influence of surface morphology on the adhesion strength of plated Cu on the build-up layer within an embedded active package

Recently, System in Package (SiP) technology is used to integrate a number of integrated circuits (ICs) enclosed in a single package or a module, which attracts a great attention from electronic industries due to its characteristics of smaller size, higher performance, lower overall cost and reduction of time to market. Based on the configurations of current SiP, there are two types of structure: (1) 2D package, such as the multi-chip package (MCP) and (2) 3D package, such as multi-chip package (MCP), stacked dies, package on package (PoP) and package in package (PiP). Although 3D interconnection by through silicon via (TSV) is beneficial to enhance the transmission of signal between ICs, but the processes are costly and are not stable enough for mass production. ITRI has developed a novel PoP structure mutated from the announced embedded active technology by semi-additive process (SAP). The purpose of this study was to enhance the reliability of the PoP by establishing an optimal process window of the chemical processes used. For achieving this, 2 pieces of 40 μm thick Ajinomoto build-up film (ABF, GX-13R) were laminated to embed a 50 um thick chip in a carrier substrate, in order to improve the adhesive strength of Cu on the ABF, different processing factors such as the pressure profiles of lamination, curing conditions, and desmear parameters were used to form various surface morphologies of the ABF, the relationships between the morphologies and the adhesion strengths were learned by a peeling test. As the experiment results showed, the adhesion strength of Cu on ABF was more significantly influenced by the surface morphology of ABF, rather than the surface roughness, and a coral morphology was believed to greatly improve the adhesion strength than the needle and plated ones.

Evaluating fine-pitch chip-on-flex with non-conductive film by using multi-points compliant bump structure

High density packaging increasingly dominates the market share in LCD highlighting the need not only to decrease the pitch of bonding joints, but also to increase the I/O numbers of driver IC for high-end display applications. However, the shortage between two adjacent electrodes is a major problem when using conventional packaging technologies. Non-conductive film (NCF) is one of the interconnection materials which are increasingly used in LCD package and flip chip technology. There are many advantages using NCF in package, such as low cost, simplified process, and low temperature process. On the contrary, NCF bonded faces a challenge of yield. In this paper, we have developed a multi-points compliant bump (MPCB) using in NCF-bonded chip-on-flex (COF) process. Evaluating the effect of temperature, time, and load on electric resistance and peeling strength. A higher peeling strength is obtained at higher bonding load, temperature, and time. This indicated that the NCF with high curing degree is sufficient to hold the interconnection joints. The changes in daisy chain after 85degC/85%RH thermal humidity storage test (THST) for 500 hrs are measured. Due to MPCB deforms in bonding process, and releases counterforce in reliability test. Experimental results show that low bonding load, high bonding temperature and high bonding time is good for reliability.