Su-Ching Chung

Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Assembly of 3D chip stack with 30μm-pitch micro interconnects using novel arrayed-particles anisotropic conductive film

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

Development of high throughput adhesive bonding scheme by wafer-level underfill for 3D die-to-interposer stacking with 30µm-pitch micro interconnections

In 3D integration, die stacking together with underfilling by capillary-type underfill are the principal processes within whole conventional assembly process. How to integrate and shorten the total process steps during assembly and increase the die-stacking yield especially for thin die stack to improve the throughput that can meet the requirement from industry will be a crucial issue. In this investigation, we proposed the high throughput adhesive bonding scheme by using wafer-level underfill material for the die-to-interposer stacking with 30μm-pitch micro interconnections. The reliability characterization of the die-to-interposer stack by such bonding scheme was implemented and confirmed. Die-to-interposer test vehicle was adopted to develop the proposed adhesive bonding scheme. The micro joints of electroplating Cu/Sn solder micro bumps joined with electroplating Cu/Ni/Au micro bumps was selected as the joining structure. There were more than 3000 bumps designed in the test vehicle. Three types of wafer-level underfill material were evaluated and selected to be the suitable processing material. The optimized die-to-interposer boding profile by wafer-level underfill were developed and determined for the purpose of high throughput in this study. After assembly process by the developed adhesive bonding scheme, reliability characterization was conducted on the die-to-interposer modules. Pre-conditioning, temperature cycling test (TCT), thermal & humidity storage test (THST) and die shear test were selected to assess reliability performance of the die-to-interposer module assembled by the proposed adhesive bonding scheme. Under the optimized bonding profile, one-die assembly could be finished less than 20 seconds, which was comparable to the process time of thermocompression bonding only. Also, the wetting and joining abilities of the micro joints were as good as those bonded by thermocompression bonding with flux and no voids were found between dies. By such adhesive bonding scheme, processes of flux cleaning and underfill dispensing and curing were no longer necessary, which could apparently enhance the throughput of die stacking. Results of reliability tests revealed that no electrical-connectivity fail and delamination happened on those die-to-interposer modules with 30μm-pitch micro interconnects after TCT of 1000 cycles and THST of 1000 hours though die shear strength showed a slight degradation less than 20%. In this investigation, the developed high throughput adhesive bonding scheme displayed the high potential that could be suitable and applicable for fine pitch 3D integration and high volume manufacturing requirements.

Effect of metal finishing fabricated by electro and Electroless plating process on reliability performance of 30μm-pitch solder micro bump interconnection

Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating or electroless plating for fine pitch solder micro bumps, its process effect on the reliability performances of micro joints still needs to be clarified from the microstructural point of view, especially for the fine pitch solder micro bump interconnections. In this study, we discussed the effect of Ni/Au metal finishing fabricated by electro- and electroless plating on the reliability properties of 30μm-pitch lead-free solder micro interconnections. Palladium layer was chosen to evaluate its influence on the reliability response of fine-pitch solder micro joints with electroless Ni/Au surface finishing. The chip-to-chip test vehicle having more than 3000 solder micro bumps with a bump pitch of 30μm was used in this study. Two types of metal finishing, electroplating Ni/Au and electroless plating Ni/Pd/Au, were chosen and fabricated on the silicon carrier. In silicon carrier, the thickness of Ni layer was 2~3 μm while that of electroplating and electroless plating Au layer was 0.5μm and 0.02μm respectively. The thickness of Pd layer within the electroless Ni/Pd/Au structure was 0.05~0.1μm. The silicon chip with a solder micro bump structure of Cu/Ni/SnAg having a thickness of 5μm/3μm/5μm was used for C2C bonding. We adopted the fluxless thermocompression process for both types of micro joints and then the chip stack was assembled by capillary-type underfill. Temperature cycling test (TCT) and electromigration test (EM) were conducted to assess the effect of metal finishing on the reliability properties of those solder micro bump interconnections. The reliability results revealed that the thickness of Au layer would apparently influence the microstructure evolution within the solder micro bump interconnection after bonding process though the micro joints with thick Au layer could pass the 1000 cycles TCT. The micro joints with complicated interface reaction resulted from the thicker Au layer might lead a negative effect on the long-term reliability properties while the Pd layer would enhance the wetting ability of solder micro bump during joining. The results of EM reliability test displayed that both types of the micro joints had excellent electromigration resistance under the testing condition of 0.08A/150°C. The activated IMC growth within the micro joint during EM testing was the major reason for this superior property. This investigated completely presented the effect of metal finishing by electro- and electroless bumping processes on the reliability properties of fine pitch solder micro bump joints.

The development of high through-put micro-bump-bonded process with non-conductive paste (NCP)

In this study, various micro-bump-bonded structures with TCB + NCP processes were evaluated and developed. A commercial available snap-cure NCP material was applied for the joining processes study. Three types of micro bumps, Cu/Ni/Sn2.5Ag, Cu/Sn2.5Ag and Cu/Ni/Au- were fabricated and bonded to achieve joint structures of Cu/Ni/Sn2.5Ag/Ni/Cu, Cu/Ni/Sn2.5Ag/Au/Ni/Cu and Cu/Sn2.5Ag/Au/Ni/Cu. Moreover, the filler trapped and void issues which associated with the TCB+NCP process were also investigated. After the evaluation, the reliability test such as moisture sensitivity test level 3 (MSL 3), temperature cycling test (TCT) and high temperature Storage (HTS) were conducted to the bonded samples. Hereafter, the failure modes with the mentioned issues were analyzed and discussed. Based on the experimental and reliability results, the optimized TCB + NCP processes with various micro-bump-bonded structures can be established. The joints electrical and reliability performance associated with the failure mode were investigated and analyzed. Finally, the characteristics of each joint connection were defined.

Low temperature bonding using non-conductive adhesive for 3D chip stacking with 30μm-pitch micro solder bump interconnections

Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chip-stacking technology have received a great number of attentions. Solder micro bumps are widely applied in high density interconnections packaging, but its bonding temperature is still high during process. During chip stacking process, high bonding temperature would lead chip damage and chip warpage induced by the mismatch of coefficient of thermal expansion among each structure within the chip. Also, warpage would cause stress concentration happened within the chip and damage the device and micro interconnections. In order to meet the purpose of low temperature bonding, we demonstrated the chip-to-chip stacking module with a bump pitch of 30um by using non-conductive film in this study. The reliability of the chip-stacking module produced by such low temperature bonding approach was also estimated. A chip-on-chip (COC) structure was used as the test vehicles. There were about 3000 bumps totally in this test vehicle. For evaluating the feasibility of adhesive bonding by NCF in fine pitch micro bumps, Cu/Ni/Au micro bumps joined with Cu/Sn solder micro bumps was conducted by using NCF in this study. After assembly process, thermal cycling test, thermal humidity storage test and high current test were carried out to evaluate the reliability performance of the micro interconnections by such low temperature bonding approach. In this investigation, the chip-on-chip stacking module with a bump pitch of 30μm by using non-conductive film was achieved. The bonding results revealed that the contact resistance of micro joints was about 100 ~ 350 MΩ. The high deviation of contact resistance was due to the non-melting contact between joined micro bump by soft tin solder. The reliability results revealed that the chip-stacking module produced by NCF could pass the reliability test of 1000 cycles of TCT and 1000 hours of THST. The results of high current test also showed that the NCF joint had excellence endurance against high current density of 5×104 A/cm2 for more than 1300 hours with an increase of contact resistance less than 2%. This study displayed that the NCF material had great potential to be applied in fine-pitch 3D chip stacking. The multi-chip stacking module with a TSV pitch of 20μm produced by NCF will also be presented in this investigation.

Low temperature bonding of 30um pitch micro bump interconnection for 3D IC stacking using non-conductive adhesive

For evaluating the feasibility of adhesive bonding by NCF (non-conductive film) in micro bump joints, three types of micro joints were adopted in this study. The structure of the type I micro joints was Cu/Ni/Au while that of the type II micro joints was Cu/Ni/Au micro bump joined with Cu/Sn solder micro bump. Both the type I and type II micro joint were bonded by using NCF. The structure of the type III micro joints were the same, but the type III micro joints were produced by eutectic bonding. For the type III micro joints, the micro gap between chips was wrapped by a capillary underfill. The bonding results revealed that the contact resistance of the NCF joints was in the range of 100 Qm ∼ 400 Qm which was higher than that of eutectic joints. Electrical continuity of micro bump interconnection was monitored by measuring the contact resistance of four-point Kelvin structure and daisy chain during reliability test. Thermal cycling test and thermal humidity storage test were conducted to evaluate the reliability performance of these three types of micro interconnections. The reliability test displayed that the reliability performance of eutectic joints was better than that of the NCF joints. The study showed that NCF joints have great potential to be applied in low temperature bonding of fine pitch 3D IC stacking.

Bonding and reliability assessment of 30 μm pitch solder micro bump interconnection with various UBM structure for 3D chip stacking

With the increased demand of multifunction in electronic device, downscaling of interconnection pitch presents an important role for the next generation electronics with high performance, small form factor, low cost and heterogeneous integration. In the current types of interconnects, solder micro bumps have received much attention due to its low cost of material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the solder micro bump joints with different kinds of UBM material will present varied reliability performances. However, which structure of solder micro bump joint shows the better reliability properties is not concluded yet until now. In this study, three-dimensional (3D) chip stacking using 30μm pitch interconnects with lead-free solder bumps and two types of UBM material is described. The reliability of solder micro bump interconnection with varied UBM material is also discussed. Assembly of the chip-on-chip test vehicle with a micro bumps diameter of 18 μm and a pitch of 30 μm was conducted. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. Two kinds of UBM layer on Si chip were selected in this study: one was single copper layer with a thickness of 8 μm and the other was Cu/Ni layer with a total thickness of 8 μm. The UBM was electro-plated on Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. During bonding process, the micro joints were formed at a peak temperature of 250 °C and the microgaps between chips were then filled by a capillary underfill cured at 150°C for 30 min. In this study, we evaluate the effect of fluxless bonding on the joining ability of solder micro bumps. The influence of underfill on the reliability of solder micro bump interconnections was estimated also. Subsequently, the chip-stacking modules were inspected by an X-ray and a scanning acoustic microscope (SAM) to determine the quality of micro joints including bonding accuracy, formation of interconnections and the percentage of voids within the underfill. Afterwards, the moisture sensitivity level 3 pre-conditioning test and temperature cycle test for 1000 cycles were performed to evaluate the reliability of solder micro bump interconnects. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation.

Development of micro-bump-bonded processes for 3DIC stacking with high throughput

Various approaches of high throughput bonding processes were investigated in the micro-bump-bonded processes for 3DIC stacking. The two-step bonding methods, TCB + reflow, TCB + post-bonding and conventional flip-chip process were evaluated in this study. Moreover, the two-step process with different TCB process times (1s, 3s and 5 s) were implemented into the first step. The partial melted joints, which were attained by TCB process, were expected to be fully bonded by the second step (reflow or post-bonding). Then, the temperature cycling test (TCT) was performed to verify reliability performance of the micro-bump-bonded interconnects. Based on the experimental and reliability results, the optimized conditions for the two-step bonding methods and a cost effective solution for the applications of 3DIC stacking can be established.