Yuchul Hwang

FAM83H mutations cause ADHCAI and alter intracellular protein localization.

Mutations in a family with sequence similarity 83 member H (FAM83H) cause autosomal-dominant hypocalcification amelogenesis imperfecta (ADH CAI). All FAM83H ADHCAI-causing mutations terminate translation or shift the reading frame within the specific exon 5 segment that encodes from Ser287 to Glu694. Mutations near Glu694 cause a milder, more localized phenotype. We identified disease-causing FAM83H mutations in two families with ADHCAI: family 1 (g.3115C>T, c.1993 C>T, p.Q665X) and family 2 (g.3151C>T, c.2029 C>T, p.Q677X). We also tested the hypothesis that truncation mutations alter the intracellular localization of FAM83H. Wild-type FAM83H and p.E694X mutant FAM83H fused to green fluorescent protein (GFP) localized in the cytoplasm of HEK293T cells, but the mutant FAM83H proteins (p.R325X, p.W460X, and p.Q677X) fused to GFP localized mainly in the nucleus with slight expression in the cytoplasm. We conclude that nuclear targeting of the truncated FAM83H protein contributes to the severe, generalized enamel phenotype.

Hygro-thermo-mechanical analysis and failure prediction in electronic packages by using peridynamics

This study presents an integrated approach for the simulation of hygro-thermo-vapor-deformation analysis of electronic packages by using peridynamics. This theory is suitable for such analysis because of its mathematical structure. Its governing equation is an integro-differential equation and it is valid regardless of the existence of material and geometric discontinuities in the structure. It permits the specification of distinct properties of interfaces between dissimilar materials in the direct modeling of thermal and moisture diffusion, and deformation. Therefore, it enables progressive damage analysis in materials or layered material systems such as the electronic packages. It describes the validation procedure by considering a particular package for each thermomechanical, hygromechanical deformation as well as vapor pressure predictions. Also, it presents results concerning failure sites and mechanisms due to hygro-thermo-vapor-deformation.

Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory

We compare three dominant mechanisms in two generations of NAND Flash main chips for mass production. In addition, we analyze the charge loss behaviors of each mechanism according to cycling times. As a result, we confirm that as NAND Flash memory is scaled down, the portion of the interface trap recovery mechanism increases and the sensitivity of cycling times also increases. In the detrapping mechanism, while the charge loss of next generation is more sensitive on cycling times, the amplitude of the charge loss is larger in the current generation. Simultaneously, when the program operation is performed, the number of electrons injected into the floating gate decreases as the physical size of the device decreases. It lowers the portion of the trap-assisted tunneling mechanism and its trend is also accelerated actively as the cycling times increase.

Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory

In this letter, we separated the corner and plane component of trap-assisted tunneling (TAT) mechanism and analyzed the retention characteristics in the worlds smallest NAND flash memory (1X-nm generation). We found that the Ea of the corner component in TAT mechanism is smaller than that of the plane component due to the higher crowding electric field and larger trap density. The extracted Ea of both the components at the highest programmed Vth level (i.e., PV3 state) is smaller than that at PV2 state since the larger number of the stored electrons in floating gate increases the electric field across the tunneling oxide layer. It reduces the energy barrier between the traps and Ea. The ratio of the corner part over the plane one is larger at highly cycled and in smaller devices. For better understanding of the abnormal retention characteristics, each failure mechanism should be accurately analyzed.

Accurate Lifetime Estimation of Sub-20-nm NAND Flash Memory

Previously, we developed a charge loss/gain model for NAND flash memory, which is taking into account various failure mechanisms. In addition, we extracted all the parameters of the new model in the highest (PV3) and lowest states (ERS). In this paper, however, the physical information for the parameters and the whole procedure of the parameter extraction are covered in detail. We also extracted the contribution rate (CR) of dominant mechanisms at the criterion of |ΔVth_Total| according to the baking temperature. The results give the physical reason for abnormal retention behaviors such as apparent activation energy (Eaa) roll-off at the PV3 state and negative Eaa at the ERS state. Using the proposed method, we extracted the accurate lifetime at room temperature in all states (PV3, PV2, PV1, and ERS). A large gap was observed in the results of the lifetime estimation, which were extracted by the conventional Arrhenius model and the proposed model. Since the proposed model takes into account the retention characteristics for various mechanisms, this model provides a much more accurate prediction for the lifetime.

Chip package interaction in micro bump and TSV structure

The purpose of this paper is chip package interaction(CPI) of fine pitch micro bump and trough silicon via(TSV). We focus on hot temperature storage(HTS) and electromigration (EM) due to its strong impact on reliability. In chip on chip (CoC) structure, Cu and Ni was used to evaluate under bump metallurgy(UBM) reliability. TSV stacked chip with Cu UBM was evaluated as well. There is no resistance degradation at CoC flip-chip structure (no TSV structure), but resistance of TSV stacked chip was increased after 1000 hours at HTS 150°C. The cause of resistance increase is intermetallic(IMC) penetration into TSV during annealing process. It strongly recommends that effective barrier metal is required to slow down IMC formation. In addition, EM test was performed to investigate resistance against current stress for small size micro bump at various current densities and temperatures. Ni UBM and Cu UBM show good EM resistance even its small size. Cu UBM shows better EM life time than that of Ni UBM due to less Joule heat generation during EM test. However, EM with TSV structure shows less lifetime due to Cu metal line damage. Finally, we demonstrate preliminary look-ahead qualification such as HTS, Preconditioning, temperature humidity bias(THB), and temperature cycle(TC) for our TSV stacked product.

Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory

In this paper, we analyzed the characteristics of dominant failure mechanisms in the erased (ERS) state of sub 20-nm NAND Flash memory with an accurate compact model. As a result, it was observed that various charge loss and charge gain mechanisms are mixed together. While the detrapping and the interface trap recovery (Nit) mechanism contribute to the charge loss, the trap-assisted tunneling (TAT) is the charge gain mechanism in the ERS state due to the negative electric field across tunneling oxide layer. At the less cycled cells, the charge gain is dominant due to the TAT mechanism. However, as increasing the cycling times, the detrapping component becomes larger by trapped carriers and the TAT component gets reduced as the detrapped electrons raise the energy level of floating gate (FG) and energy barrier of tunneling oxide layer. Therefore, the charge loss becomes dominant at increased cycling times.

Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

We observed an increase of Vth by read disturbance mechanism at programmed threshold voltage state (PV1) and erase state (ERS) states in retention characteristics of sub-20 nm NAND flash main-chip. We also confirmed that the charge gain behavior by read disturbance has dependency on the number of read and cycling operations. As a result, we quantitatively modeled read disturbance mechanism by the amount of final ΔVth and deterioration coefficient α which is related to the number of read operation times. It was also observed that those parameters increase with increasing cycling times and have larger value at ERS state than that at PV1 state.

Probability Level Dependence of Failure Mechanisms in Sub-20 nm NAND Flash Memory

We extracted final ΔV_th, time constant, and activation energy (E_a) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of V_th cumulative probability distribution. As a result, we confirmed that at lower P level, the final ΔV_th of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final ΔV_th of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger E_a at high P level, whereas the E_a of detrapping mechanism decreases because of barrier lowering effect.

The reproducibility improving method of systemlevel ESD test through operating program workload analysis

It is well known that the system-level ESD tests suffer from poor reproducibility. Reproducibility problems appear in various cases; in different systems and the different ESD guns, even if the ESD test conducted using the same systems and ESD guns. This paper is proposed the method which can improve the reproducibility of the system-level ESD test at the same system. The operating state of DRAM is very important factor to the ESD failure level by measuring the signals of memory modules during an ESD event. The soft failure is observed when there is a signal toggling during an ESD event. Through the experiment of program workload, it is confirmed there is a strong correlation between the program workload and the reproducibility of ESD test result. The reproducibility of the system-level ESD test can be improved by maximizing the program workload.