Duckseoung Kang

Activation Energies

The conventional temperature-accelerated lifetime test method of NAND Flash memory does not follow the Arrhenius model, as various failure mechanisms occur concurrently. We completely separated three main failure mechanisms and extracted each activation energy (Ea) value in three generations (A, B, C) of advanced NAND Flash memory. We compared and analyzed each value of Ea of the three main mechanisms with different device generations and cycling times. The results confirmed that each failure mechanism follows the Arrhenius law. The extracted Ea values of the detrapping mechanism were almost the same (Ea ~ 1.0 eV) regardless of the generation or the cycling times because they are determined by the rate of change of the detrapping probability of each trapped electron according to the baking temperature, not the surface area or trap density. However, the Ea value of the trap-assisted tunneling (TAT) mechanism is dependent on the generation and cycling times. Both the dominant trap energy levels and the average distance between the traps in the oxide layer have a strong impact on the Eavalue of the TAT mechanism. The interface trap recovery mechanism has very small time-constant (τ), and its activation energy is very small (Ea ~ 0.2 eV).

(E_{a})

We compare three dominant mechanisms in two generations of NAND Flash main chips for mass production. In addition, we analyze the charge loss behaviors of each mechanism according to cycling times. As a result, we confirm that as NAND Flash memory is scaled down, the portion of the interface trap recovery mechanism increases and the sensitivity of cycling times also increases. In the detrapping mechanism, while the charge loss of next generation is more sensitive on cycling times, the amplitude of the charge loss is larger in the current generation. Simultaneously, when the program operation is performed, the number of electrons injected into the floating gate decreases as the physical size of the device decreases. It lowers the portion of the trap-assisted tunneling mechanism and its trend is also accelerated actively as the cycling times increase.

of Failure Mechanisms in Advanced NAND Flash Cells for Different Generations and Cycling

In this letter, we separated the corner and plane component of trap-assisted tunneling (TAT) mechanism and analyzed the retention characteristics in the worlds smallest NAND flash memory (1X-nm generation). We found that the Ea of the corner component in TAT mechanism is smaller than that of the plane component due to the higher crowding electric field and larger trap density. The extracted Ea of both the components at the highest programmed Vth level (i.e., PV3 state) is smaller than that at PV2 state since the larger number of the stored electrons in floating gate increases the electric field across the tunneling oxide layer. It reduces the energy barrier between the traps and Ea. The ratio of the corner part over the plane one is larger at highly cycled and in smaller devices. For better understanding of the abnormal retention characteristics, each failure mechanism should be accurately analyzed.

Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory

In this paper, we analyzed the characteristics of dominant failure mechanisms in the erased (ERS) state of sub 20-nm NAND Flash memory with an accurate compact model. As a result, it was observed that various charge loss and charge gain mechanisms are mixed together. While the detrapping and the interface trap recovery (Nit) mechanism contribute to the charge loss, the trap-assisted tunneling (TAT) is the charge gain mechanism in the ERS state due to the negative electric field across tunneling oxide layer. At the less cycled cells, the charge gain is dominant due to the TAT mechanism. However, as increasing the cycling times, the detrapping component becomes larger by trapped carriers and the TAT component gets reduced as the detrapped electrons raise the energy level of floating gate (FG) and energy barrier of tunneling oxide layer. Therefore, the charge loss becomes dominant at increased cycling times.

Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory

We observed an increase of Vth by read disturbance mechanism at programmed threshold voltage state (PV1) and erase state (ERS) states in retention characteristics of sub-20 nm NAND flash main-chip. We also confirmed that the charge gain behavior by read disturbance has dependency on the number of read and cycling operations. As a result, we quantitatively modeled read disturbance mechanism by the amount of final ΔVth and deterioration coefficient α which is related to the number of read operation times. It was also observed that those parameters increase with increasing cycling times and have larger value at ERS state than that at PV1 state.

Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory

We extracted final ΔV_th, time constant, and activation energy (E_a) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of V_th cumulative probability distribution. As a result, we confirmed that at lower P level, the final ΔV_th of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final ΔV_th of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger E_a at high P level, whereas the E_a of detrapping mechanism decreases because of barrier lowering effect.

Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

This paper provides the simple design guideline of negative capacitance FET (NCFET). By considering average slope in polarization of a ferroelectric (FE) material according to electric field, simple design guideline was suggested to find the optimal thickness of FE material in NCFET where SS becomes 60 mV/dec. As the thickness of FE material increases, subthreshold swing (SS) becomes improved until limit condition occurs.

Probability Level Dependence of Failure Mechanisms in Sub-20 nm NAND Flash Memory

Mixed mode TCAD simulation using hydrodynamic transport model was performed for SRAM cell composed of 90Å silicon Bulk-FinFET. In case of worst-case trapping combination in SRAM and at high temperature (375K), read static noise margin (RSNM) is reduced by 16.1% compared to the case with empty trap and at 300K. In addition, regarding statistical variability including work function variation (WFV), random dopant fluctuation (RDF), and line-edge roughness (LER), minimum operation voltage of SRAM is about 0.36 V when minimum RSNM is 20 mV.

Simple design guideline for negative capacitnace FET using ferroelectric materials

In this paper, we investigate the impact of line edge roughness (LER) combined with random telegraph noise (RTN) induced by carrier trapping on threshold voltage and stability of SRAM cells with 70 Å nanowire FETs. It is found that LER combined with RTN boosts VT fluctuation more than the case with the single noise source. Its effect can limit aggressive scaling seriously.

Minimum operation voltage of 6T-SRAM cell composed of 90Å bulk-FinFET considering oxide trap, high temperature, and variability

In the above paper (ibid., vol. 34, no. 9, pp. 1139-1141, Sep. 2013), the corresponding authors are not correctly indicated. Hyungcheol Shin is also an author to whom correspondence for the published letter should be directed toward.