Dong Hua Li

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon–oxide–nitride–oxide–silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler–Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30×70 nm2 (L×W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7 nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.

Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory

A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F2 size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

Channel doping concentration and fin width effects on self-boosting in NAND-type SONOS flash memory array based on bulk-FinFETs

In performing the program operation of the NAND-type flash memory array, the program inhibition is made possible by self-boosting of the channel potential. However, the high program voltage may cause the unwanted program operations in the vicinity: charge redistributions in the adjacent cells sharing either the same bit-line (BL) or the same word-line (WL). In this work, the dependences of self-boosting of the channel potential on process variable and device dimension have been investigated by a 3-D device simulation. Channel doping concentration and fin width have been controlled as the variables. The self-boosting effect has shown an optimum point at a channel doping concentration of 6×1017 boron atoms/cm3, and it decreases monotonically as the silicon fin width becomes thicker.

Effects of equivalent oxide thickness on bandgap-engineered SONOS flash memory

In order to implement more advanced nonvolatile memory device, many studies have been devoted to improve program/erase speed, endurance, and retention characteristics of nitride-based SONOS flash memory. As the CMOS device size shrinks down, the oxide-nitride-oxide (ONO) multi-layer where charge storage takes place in discrete traps in the silicon nitride layer needs the optimization of thickness and material properties in order for the SONOS flash device to follow the CMOS technology development trend. However, the retention characteristics of SONOS flash memory degrade with the scaling of tunnel oxide, although the program/erase speed is enhanced with the decrease of tunnel oxide thickness. To overcome this problem, we adopted the SONOS structures with bandgap-engineered tunnel oxide layer. The bandgap- engineered SONOS flash memory provides faster erase speed and better retention characteristics than the conventional SONOS flash memory in our previous work. In order to identify the limitation of the equivalent oxide thickness (EOT) of the ultra-thin ONO barrier which replaces the single tunnel oxide layer in the conventional SONOS structures, we have controlled the EOT of the ONO barrier by the standard CMOS process and investigated their effects on the program/erase speed, memory window, and data retention characteristics of the bandgap-engineered SONOS flash memory device. As a result, the experimental data show that the ONO has a degree of freedom in the thickness of each layer but the data retention loss should be still considered. The SONOS flash memory with bandgap engineering by adopting the ONO barrier instead of single tunnel oxide layer should have a lower limit of 3 nm as the EOT for both performance and reliability.

Improvement on erase characteristics of SONOS flash memory by bandgap engineering of tunnel oxide

We comparatively analyze the erase speed and long-term reliability between the conventional SONOS flash memory and the bandgap engineered SONOS flash memory devices. As a result, the bandgap engineered SONOS device is indeed proven to provide faster erase speed and better long-term data retention characteristics than the conventional SONOS device.

Memory characteristics improvement encouraged by the shape of narrow drain in cone SONOS memory structure

We have proposed cone SONOS memory structure previously. The point of the structure is field concentration effect in two directions. Among the two, concentration of source to drain direction is critical in program operation. Simulation result shows the shape of narrow drain leads to great memory performance. Fabricated structure shows the same results. In this report, simplified program simulation result is presented and great injection characteristics is shown by comparison with cylinder structure.

Comparative analysis of trap-based program/erase behaviors with tunnel dielectric for SONOS flash memory

In this study, we comparatively analyze the trap-based memory operation characteristics with tunnel dielectric in Oxide-Nitride-Oxide (ONO) structure. Detailed analysis is focused on the difference between single and bandgap engineered (BE) tunnel dielectric by comparing the program/erase (P/E) and charge retention behaviors. As a result, bandgap engineered tunnel dielectric structure embodies both fast P/E speed and long-term charge retention characteristics which exhibit a possible solution for performance optimization in SONOS flash memory device.

Highly scalable vertical bandgap-engineered NAND flash memory

In this work, highly scalable charge trap flash (CTF) memory with bandgap-engineered storage node and vertical channel is proposed. Due to the compact cell layout without individual junction contacts, NAND flash memory has the most suitable architecture for mobile data storage media. In other to achieve even higher integration density, two NAND flash memory cells in the conventional sting are put together to have a common vertical channel as shown in Fig. 1(a). The biggest merit in this array feature is that half-level reduction in footprint can be achieved by using the sidewall control gates as shown in Fig. 1(b). Due to the vertical channel, the channel length can be simply controlled by anisotropic dry etch, which suppresses short channel effects (SCEs) effectively and enlarges the sensing margin. Fig. 1(c) shows the schematic view of the array with circuit symbols. Also, in this novel flash memory, the memory storage node uses a bandgap-engineered (BE) multi-layer, where the oxide-nitride-oxide triple-layer replaces the tunnel oxide to improve the performances in operations [1–3]. The process architecture for fabricating the vertical BE-NAND flash memory is summarized in Fig. 2. The fin structures in both bitline (BL) and wordline (WL) directions have been formed by sidewall spacer patterning [4]. Among the several possible combinations of materials [5–6], nitride (Si3N4) and TEOS are used for the sidewall spacer and the supporting dummy pattern, respectively. Fig. 3 and 4 shows the process flow for Si fin constructions in both directions. After the fin consisted of Si-STI alternating pillars is formed in the WL direction, ONONO (20/20/20/60/60 Å) multi-layer is deposited. All the oxide layers were deposited by medium temperature oxidation (MTO) in an ambient of N2 160 sccm and DCS 40 sccm. The tunneling and storage nitride layers were deposited by LPCVD in the ambient of NH3 30 sccm/DCS 10 sccm/750 °C and NH3 100 sccm/DCS 30 sccm/785 °C, respectively. Subsequently, physically separated sidewall control gates used as WLs are formed by etch-back process. Fig. 5(a) through (c) show the images for fin structures and top view of the vertical BE-NAND flash with independent sidewall gates. After ILD/CMP/metallization/alloy, the fabrication is completed.

Scaling behaviors of silicon-nitride layer for charge-trapping memory

The authors investigate the scaling behaviors of a silicon-nitride layer for use in a charge-trapping memory device according to dimension downscaling of the memory-device cells. As is known, charge storage takes place in discrete traps in the silicon-nitride layer. In this study, a 5-nm-thick charge-storage layer in the conventional oxide-nitride-oxide device is investigated and shows considerable trap-based memory characteristics, but encounters a retention problem. Therefore, they adopt a modulated tunnel barrier to replace the single tunnel oxide so as to improve the charge-retention property. As a result, experimental results show excellent memory program/erase operation behaviors and indicate further scalability of the charge-storage layer compared to the conventional oxide-nitride-oxide device.

Enhancement of erase speed using silicide drain in nanowire SONOS NAND flash memory

Since recent mobile electronic devices have started to adopt NAND flash memory as their main data storage device, the demand for low cost and high density NAND flash memory has been rapidly increasing. As a promising candidate, nanowire SONOS NAND flash memory array has been introduced and reported for highly scalable device structure [1], [2], [3]. However, since it is hard to bias floating body of memory cells, a reliable erase operation is not easy for nanowire NAND flash memory technology. So, a method which uses the hole current generated by GIDL near the select gate has been proposed for erase operation of this structure [4]. In this paper, we propose a new method for significantly enhancing the erase speed of nanowire SONOS NAND flash memory through the use of silicide drain.