Yufeng Xie

A 3D RRAM using stackable 1TXR memory cell for high density application

This paper reports a novel 3D RRAM concept using stackable multi-layer 1TXR memory cell structure for future high density application. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Corresponding operation algorithm is put forward for the first time, which can inhibit mis-write and mis-read caused by sneaking current and reduce power consumption.

Novel RRAM programming technology for instant-on and high-security FPGAs

This paper introduces a novel RRAM programming technology to improve the security and shorten the startup time of FPGAs. A 9T2R nonvolatile SRAM (nvSRAM) cell is comprised of two 1T1R RRAM cells and a standard 6T SRAM cell on a single die by integrating the RRAM technology into the standard logic process. The 9T2R cell stores the configuration bit in the two 1T1R cells in complementary style and can quicky read it into the SRAM cell in less than 300 ps at power-on. Besides, the proposed RRAM programming technology excels SRAM in dynamic reconfiguration for less interrupt time or small area overhead. A testchip of a 2-input LUT with the proposed RRAM programming technology has been demonstated in 0.13µm logic technology.

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security

A 64-kB logic resistive random access memory (RRAM) chip for physically secure key storage is presented. The chip has security features of resisting fully invasive attacks such as deprocessing and microscopy observation, resisting side-channel attacks by providing symmetrical power and timing read signals, resisting malicious writing by a reduced write protection scheme with feedback, and resisting data interception attack across pin boundary by the ability of on-chip integration with logic platform. The chip is fabricated in a 0.13-μm standard logic process and implemented as the key storage for a demonstrative information security platform with a MIPS-based cryptoprocessor. Experiments of reverse engineering and mechanism investigation proved the fully invasive attack-resistant features, and experiments emulating side-channel attacks revealed no difference between 0 and 1. Experiments also showed that the information security platform could correctly encrypt and decrypt with the RRAM key storage. The proposed chip has obvious advantage on area, power, and security features for embedded key storage compared with its Antifuse counterpart.

A 0.13µm 8Mb logic based Cu x Si y O resistive memory with self-adaptive yield enhancement and operation power reduction

A 0.13μm 8Mb CuxSiyO resistive memory test macro with 20F2 cell size is developed based on logic process for the first time. Smart and adaptive assist write and read circuit are proposed and verified in order to fix yield and power consumption issues from large write speed and high temperature resistance variation. SAWM (self-adaptive write mode) helps to enlarge Roff/Ron window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and large power consumption is eliminated after set success. SARM (Self-adaptive read mode) improves read bit yield from 98% to 100% at 125°C. The typical access time of on-pitch voltage sensing SA(sense amplifier) is 21ns and high bandwidth throughput is supported.

Nonvolatile SRAM cell based on Cu x O

A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows the unused blocks of SRAM to be powered down to save energy.

A logic 2T gain cell eDRAM with enhanced retention and fast write scheme

A logic-process embedded DRAM with 2T multi-Vth PMOS gain cell with one high-Vth for retention enhancement and one low-Vth transistors for fast read speed is proposed. To improve the write speed, the write back step and sense step are separated, and the write before sense schemes are adopted to improve write speed and suppress the noise disturbance to adjacent bitlines. The simulation results illustrate that the write cycle of memory is 3ns which corresponding to 333MHz operating frequency. The cell size is 64F2 and is 40% of SRAM in the same process generation.

64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage

A 64 Kb logic Resistive Random Access Memory (RRAM) test chip for encryption keys storage is presented for the first time. The excellent security features of resisting physical attacks and side-channel attacks are theoretically analyzed and experimentally proved. The chip is fabricated in 0.13μm standard logic process, and can directly integrate with encryption logic circuits of information systems.

A physically-secure write scheme of Multi-time Programmable RRAM for critical information storage

A physically-secure write scheme of Multi-time Programmable (MTP) RRAM for critical information storage is proposed and analyzed. The on-chip storage circuit can prevent physical attacks and illegal or malicious write operation. It improves the security level of existing MTP RRAM storage arrays by introducing an extra column storing protect-bits and using the address scrambling circuits. The proposed circuit is designed based on the RRAM which is logically compatible, so it provides higher resistance over physical attacks. And the MTP structure enables users with high priorities to change the stored security information.

Adaptive Block level management for hybrid main memory

This paper proposes a PCM hybrid main memory management scheme called APABL (Adaptive PRAM aware Block-based LRU). Proposed scheme takes DRAM as the first memory and PCM as the spare memory. Only data evicted from DRAM is to be written into PCM. Our scheme can reduce both the access times to PCM and SSD without performance loss. Thus, it can also benefit the mobile computer.

A BIST scheme for high-speed Gain Cell eDRAM

A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set architecture (ISA) and hardware. A 4-stage pipeline for instruction execution makes at-speed test possible. Various kinds of tests, including single-address test, traversal test and refresh test, can be performed by executing different instruction combinations. An 8KB Gain Cell memory with the BIST is fabricated in 0.13µm CMOS technology. Silicon measurement on ATE shows that the BIST can perform at-speed test and measurement types mentioned above.