Yuh-Jier Mii

VLSI on-chip interconnection performance simulations and measurements

We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or “interconnects.” Performance can be affected by wiring geometry, materials, and processing details, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical properties, pulse propagation, and CPU cycle-time estimation, with particular attention to potential advantages of advanced materials and processes for wiring of high-performance CMOS microprocessors. Detailed performance improvements are presented for migration to copper wiring, low-e dielectrics, and scaled-up interconnects on the final levels for long-line signal propagation.

Experimental high performance sub-0.1 /spl mu/m channel nMOSFET's

Very high performance sub-0.1 /spl mu/m channel nMOSFETs are fabricated with 35 /spl Aring/ gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V/sub dd/=1.5 V is recorded from a 0.08 /spl mu/m channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f/sub T/) of a 0.08 /spl mu/m channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 /spl mu/m channel device. Good subthreshold characteristics are achieved for 0.09 /spl mu/m channel devices with a source-drain halo process.<<ETX>>

Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide

Very-high-transconductance 0.1 mu m surface-channel pMOSFET devices are fabricated with p/sup +/-poly gate on 35 AA-thick gate oxide. A 600 AA-deep p/sup +/ source-drain extension is used with self-aligned TiSi/sub 2/ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices.<<ETX>>

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.

0.1 mu m CMOS and beyond

As CMOS scaling is approaching 0.1 mu m channel length, the authors examine a number of key device and technology issues which will ultimately determine the limit of room temperature scaling. High speed and high transconductance (750 mS/mm for n, 400 mS/mm for p) sub-0.1 mu m nMOSFET and pMOSFET devices have recently been demonstrated. P/sup +/ polysilicon gate was used on 35 AA gate oxide without boron penetration. Very low series resistances (R/sub sd/=250 Omega - mu m for nMOSFET and 500 Omega - mu m for pMOSFET) are achieved with 500-700 AA-deep n/sup +/ and p/sup +/ source-drain extensions. These results indicate that it is possible to scale CMOS devices to 0.1 mu m channel length. Beyond 0.1 mu m, however, conventional CMOS performance at room temperature levels off subject to off-current and threshold voltage requirements. A number of possibilities for further performance enhancement, such as SOI, SiGe channel, double-gate device, and low temperature CMOS are discussed.<<ETX>>

Reliability imposed design aspects of submicrometer polysilicon-emitter bipolar transistors

The device reliability of narrow poly-emitter bipolar transistors with very shallow junctions is studied experimentally. The excess base current due to nonuniform poly doping, which is typically seen in such devices, is found not to accelerate device degradation. The lower doping at the emitter edge due to known perimeter depletion and emitter plug effects (PPEs) leads to a reduced increase in base current per perimeter length with stress. The results show that bipolar device scaling can probably be pursued to a point where PPEs start to appear, and that lateral emitter grading is effective in improving the device reliability.<<ETX>>

HfSiON Gate Dielectric for 45nm Node Low-Power Device

A 1.4 nm EOT stack film of HfSiON with interfacial oxide layer (IL) is demonstrated with excellent electrical characteristics and reliability for 45 nm node low-power technology. Mobility comparable to SiON is achieved along with adequate nMOS PBTI lifetime, TDDB lifetime, and breakdown voltage (VBD). For the first time, we report lower VBD for the HfSiON stack film despite of 3 orders gate leakage reduction compared to the same EOT SiON. It is attributed to IL breakdown in the proposed two-step breakdown mechanism. This possibly limits the scalability of such a stack film. On the other side, over-drivability of HfSiON with thick underlying oxide boosts input/output (I/O) device performance significantly