Mamoru Terauchi

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

SOI CMOS with gate-body connection (DTMOS) and body bias controlled SOI pass-gate logic (BCSOI pass-gate) take advantage of individually isolated SOI device active area and reduce threshold voltage by controlling each device body bias. Hence, they enjoy higher speed than circuits based on fixed low threshold voltage. The direct body bias control used in previous work suffers from leakage current at supply voltage higher than 0.8V due to drain-body junction leakage. A practical circuit technology that offers the highest speed, lowest operation voltage and stable operation under wide supply voltage demonstrates performance with an ALU macro using this technology.

Technology trends of silicon-on-insulator-its advantages and problems to be solved

Recent progress in SOI technology is reviewed and problems which need be solved are discussed. Emphasis is placed on the substrate floating effect, for which the bandgap engineering method is proposed for the first time. It is demonstrated that Si-Ge formation in the source region can improve the drain breakdown voltage significantly.<<ETX>>

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFETs. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFETs exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.

0.5 V SOI CMOS pass-gate logic

Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.

Formation of SiGe Source/Drain Using Ge Implantation for Floating-Body Effect Resistant SOI MOSFETs

SiGe was formed by Ge implantation into silicon on insulator (SOI) substrates with the dosage range from 0.5 to 3 x 10 16 cm -2 and subsequent annealing in N 2 . The implantation dosage dependence of the crystalline quality, bandgap and sheet resistance of the SiGe layers are investigated. The implantation damage for Ge dosage up to 1 x 10 16 cm -2 can be removed at a temperature as low as 700°C. A SiGe crystalline network is formed by the annealing at the same time. With a Ge dosage of 1 x 10 16 cm -2 or more, bandgap narrowing of the SiGe layer was detected. Sheet resistances of SiGe N + and P + layers gradually increase for higher Ge dosage. SOI MOSFET characteristics in terms of the floating-body effect with the SiGe source/drain layers are presented. The bandgap narrowing suppresses the floating-body effect of fully depleted SOI MOSFETs, while maintaining the reverse leakage current of the p-n junction between the source/drain and channel at a low level.

Selectable Logarithmic/Linear Response Active Pixel Sensor Cell with Reduced Fixed-Pattern-Noise Based on Dynamic Threshold MOS Operation

A selectable logarithmic/linear response active pixel sensor cell with reduced fixed-pattern-noise is proposed. It is composed of four dynamic threshold metal-semiconductor-oxide field-effect transistors (DTMOSs), which have inherently fewer characteristic fluctuations than conventional bulk counterparts. Therefore this proposed active pixel sensor cell is expected to reduce fixed-pattern-noise as compared with that of a device composed of bulk metal-oxide-semiconductor field effect transistors (MOSFETs) without any external noise reduction circuitry particularly in the logarithmic response mode. The effectiveness of the proposed sensor cell is partly experimentally verified using test devices that simulate the readout portion of the proposed sensor cell.

Suppression of the floating-body effects in SOI MOSFETs by bandgap engineering

The floating-body effects, which are regarded as the most critical issues in applying Silicon-On-Insulator (SOI) devices to actual LSIs, can be suppressed by the reduction in bandgap energy in the source region. In addition to an increase in the drain breakdown voltage, the suppression of both kinks in I/sub d/-V/sub d/ characteristics and threshold voltage shift with an increase in drain voltage are achieved in sub-quarter micron Nch thin-film SOI MOSFETs.

Impact of Forward Substrate Bias on Threshold Voltage Fluctuation in Metal–Oxide–Semiconductor Field-Effect Transistors

The effect of forward substrate (body) bias on threshold voltage (Vth) fluctuation in metal–oxide–semiconductor field-effect transistors (MOSFET) and its device parameter [e.g., gate length, substrate impurity concentration, gate oxide thickness (effective oxide thickness), etc.] dependence are investigated using a charge-sharing model. It is predicted that, through the application of a forward substrate bias of 0.5 V, Vth fluctuation is suppressed by up to 20% and the device parameter sensitivity of Vth is reduced in sub-100-nm devices. An experimental result demonstrating the effect of forward substrate bias on Vth fluctuation suppression is also presented.

Evaluation of 0.3.MU.m Poly-Silicon CMOS Circuits for Intelligent Power IC Application.

In this paper, we report on the fine device performance of a 0.3 µm gate length polysilicon complementary metal-oxide-semiconductor (CMOS). The breakdown voltage of 0.3 µm n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) devices exceeds 6 V, which is higher than that of NMOSFET devices on separation by implanted oxygen (SIMOX) wafer. The drain current of a 10 µm channel width device is 540 µA, which is one-fifth of that of NMOSFET on SIMOX. The leakage current is less than 10-11 A/µm, when the gate voltage is below 0 V. The S-factor is 125 mV/dec, and the threshold voltage is 0.4 V. Therefore the ON/OFF current ratio is greater than 107. A delay time of 1 ns is achieved in polysilicon NAND rings. Hence, it is ascertained that the polysilicon CMOS is applicable for the fabrication of control and protection circuits on power devices.

Temperature dependence of the subthreshold characteristics of dynamic threshold metal-oxide-semiconductor field-effect transistors and its application to an absolute-temperature sensing scheme for low-voltage operation

In this report the author proposes an absolute-temperature sensing scheme based on the temperature dependence of the subthreshold current–voltage characteristics of dynamic threshold metal–oxide–semiconductor (DTMOS) field-effect transistor devices. The proposed sensing scheme requires neither a voltage higher than 0.5 V nor initial precise calibration. It is suitable for silicon-on-insulator (SOI) circuits based on the SOI technology using an SOI substrate, but it can also be easily applied to bulk MOS devices.