Yumi Hayashi

Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond

Silicide-cap for Cu interconnects is promising for enhancing electromigration (EM) performance for 32 nm-node and beyond. But the trade-off properties of silicide-cap between line resistance and EM lifetime remain to be resolved. Increasing of line resistance is caused by Si diffusion in Cu line. So, we focused on Ti barrier metal (BM), which diffuses in Cu line, and applied it in combination with silicide-cap, in order to keep Si stable at the surface of Cu line. As a result, we achieved EM median time-to-failure (MTF) 100 times longer than that of the sample w/o silicide-cap and Ta-BM while line resistance is kept lower. Activation energy (Ea of EM of 1.45 eV is achieved.

Impact of oxygen on Cu surface for highly reliable low-k/Cu interconnects with CuSiN and Ti-based barrier metal

A trade-off property of CuSiN between EM improvement and line resistance increase was resolved by a breakthrough that leaves oxygen at grain boundary of Cu line surface before CuSiN formation. Then, the combination of CuSiN and Ti-rich TiN (Ti(N)) barrier metal (-BM) was applied. Oxygen left by weakening process strength of CuOx reduction lowered line resistance, because Si diffusion causing line resistance increase was controlled by the oxygen at grain boundary. Low-damage process of CuOx reduction also improved voltage ramp dielectric breakdown (VRDB) property. Excellent EM performance brought about by CuSiN was kept by the combination with Ti(N)-BM, because the oxygen made Si and Ti distributions uniform at grain boundary of Cu surface by forming Ti-silicide. Cu atom transport that caused EM failure was suppressed throughout grain boundary of Cu surface.

Process liability evaluation for beyond 22nm node using EUVL

Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22- nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer process for device manufacture at the 22-nm node and beyond.

Control of Resistance by Oxide on the Surface of Cu Interconnects With CuSiN and Ti-based Barrier Metal

To achieve both low line resistance and high electromigration (EM) reliability, CuSiN was formed on CuxO, which was purposely left on the Cu interconnect. Oxide on the Cu surface effectively suppressed Si diffusion into the Cu line: this diffusion had, in the absence of the oxide, appeared during CuSiN formation and increased line resistance. EM reliability, however, was degraded in the case of Ta barrier metal (BM). The degradation occurred because the number of Cu-Si bonds decreased, and the number of Si-O bonds increased. To counteract this, Ti-based BM was used in combination with CuSiN formed on CuxO [CuSiN(Cux O)], because Ti is uniformly distributed in Cu grain boundaries on the Cu surface when Ti is used together with CuSiN, and Ti oxide is preferentially formed to Si oxide. As a result, the combination of CuSiN(CuxO) and Ti-based BM successfully retained the EM improvement brought about by CuSiN, whereas line resistance remained low. We have found a new solution that achieves compatibility between low line resistance and high EM reliability with ease by forming CuSiN on a CuxO surface rather than by performing a sensitive adjustment of CuSiN formation.

Impact on Electromigration Performance of Combining CuSiN and Ti-Barrier Metal in Cu Interconnects

CuSiN and Ti-barrier metal (BM) were used in combination to resolve the tradeoff of CuSiN between resistivity and electromigration (EM) performance. Two types of CuSiN were prepared for this experiment. The first type, called CuSiN(h), was a thick layer and improved EM lifetime, but excess Si appeared during the formation of CuSiN(h) and diffused into the Cu line. Consequently, the resistivity was high. The second type, called CuSiN(l), exhibited no Si diffusion in the Cu line, but there was no improvement in EM performance in the case of Ta-BM. Although using CuSiN(h) and Ti-BM in combination slightly mitigated the resistivity increase caused by CuSiN(h), the extent of mitigation was insufficient, and resistivity remained high. On the other hand, the combination of CuSiN(l) and Ti-BM provided the ideal distribution of Si and Ti for high EM performance: specifically, Si and Ti were uniformly distributed along grain boundaries on the Cu surface. As a result, the median time-to-failure due to EM was about two orders longer as compared with the Ta-BM sample without CuSiN, whereas resistivity remained low. In EM testing, Cu atom transport was suppressed throughout the grain boundaries on the Cu surface, and the activation energy was 1.45 eV.

Investigation of PD-CU-SI metallic glass film for hysterisis-free and fast response capacitive mems hydrogen sensors

We show that PdCuSi metallic glass (MG) is a promising material for Pd-based capacitive MEMS hydrogen sensors, reducing both hysteresis and response time of the sensing operation. Firstly, we demonstrate that the fabricated PdCuSi MG film exhibits no hysteresis during hydrogen absorption and desorption. Drastic reduction of the response time is also shown. We also show that, to eliminate the hysteresis and to reduce the response time, PuCuSi needs to be MG, not microcrystal. Secondly, based on the measured strain property, we show that the capacitive sensing scheme has advantage in sensing low concentration hydrogens.

Evaluation of gas permeability for micro-scale thin polymer film with encapsulated MEMS damped oscillator

We present a practical method to evaluate gas permeability for thin polymer films using an encapsulated micro-electro-mechanical-system (MEMS) oscillator. Previously, we have developed a hermetic thin-film dome structure for RF-MEMS tunable capacitor, using conventional back-end-of-the-line (BEOL) processes. The dome is made of multiple layers including a polymer film, whose gas permeability is an important factor with respect to productivity and reliability. So far, it had been difficult to evaluate the gas permeability for such small and thin polymer films with sub-millimeter diameter and micron-scale thickness. In this evaluation method, the pressure dependence of air-damping oscillation is used to measure the permeability. As a demonstration, we carried out a permeability measurement of a 0.5-mm-diameter dome sealed with a thin (1 μm) polymer film. The resulting permeability coefficient is found to be 1×10-16 mol/m/Pa/s, at room temperature.

Manufacturability of 2x-nm devices with EUV tool

Due to the promising development status of EUVL as a practical lithography technology for the 2x-nm node, we are continuing to evaluate its process liability using the EUV1 at Selete, which has an Off-Axis illumination capability. The resolution limit of the EUV1 for L&S patterns is currently 18 nm for dipole illumination, and 16 nm for aggressive dipole illumination. This study examined the critical points of EUVL for device manufacturing through wafer processes. The yield obtained from electrical measurements indicates the maturity of the technology, including the resist process, the tool, and the mask. Optimization of the resist and RIE processes significantly improved the yield. The final yields obtained from electrical measurements were 100% for hp 30 nm, 70% for hp 28 nm, and 40% for hp 26 nm. These results demonstrate EUV lithography to be a practical technology that is now suitable for 2x nm semiconductor manufacture.