Yun-Hyuck Ji

Gate-first high-k/metal gate DRAM technology for low power and high performance products

It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.

The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks

The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS analysis. From the electrical and physical analysis, we verified that the flat band voltage was shifted due to an arsenic dipole formation at high-k/metal interface. The negative shift of 480mV was obtained with the optimized arsenic ion implant condition.