Yung-Chen Lin

High speed graphene transistors with a self-aligned nanowire gate

Graphene has attracted considerable interest as a potential new electronic material. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co2Si–Al2O3 core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm−1) and transconductance (1.27 mS μm−1) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of fT = 100–300 GHz, with the extrinsic fT (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic fT of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths.

High-frequency self-aligned graphene transistors with transferred gate stacks

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits.

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H(2)O(2)) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H(2)O(2)) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and renucleate on the sidewalls of nanowires to initiate new etching pathways to produce a porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 to 30 m(2) g(-1) and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy.

Sub-100 nm channel length graphene transistors

Here we report high-performance sub-100 nm channel length graphene transistors fabricated using a self-aligned approach. The graphene transistors are fabricated using a highly doped GaN nanowire as the local gate with the source and drain electrodes defined through a self-aligned process and the channel length defined by the nanowire size. This fabrication approach allows the preservation of the high carrier mobility in graphene and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords transistor performance not previously possible. Graphene transistors with 45-100 nm channel lengths have been fabricated with the scaled transconductance exceeding 2 mS/μm, comparable to the best performed high electron mobility transistors with similar channel lengths. Analysis of and the device characteristics gives a transit time of 120-220 fs and the projected intrinsic cutoff frequency (f(T)) reaching 700-1400 GHz. This study demonstrates the exciting potential of graphene based electronics in terahertz electronics.

High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.

Top-gated graphene nanoribbon transistors with ultrathin high-k dielectrics.

The integration ultrathin high dielectric constant (high-k) materials with graphene nanoribbons (GNRs) for top-gated transistors can push their performance limit for nanoscale electronics. Here we report the assembly of Si/HfO(2) core/shell nanowires on top of individual GNRs as the top-gates for GNR field-effect transistors with ultrathin high-k dielectrics. The Si/HfO(2) core/shell nanowires are synthesized by atomic layer deposition of the HfO(2) shell on highly doped silicon nanowires with a precise control of the dielectric thickness down to 1-2 nm. Using the core/shell nanowires as the top-gates, high-performance GNR transistors have been achieved with transconductance reaching 3.2 mS microm(-1), the highest value for GNR transistors reported to date. This method, for the first time, demonstrates the effective integration of ultrathin high-k dielectrics with graphene with precisely controlled thickness and quality, representing an important step toward high-performance graphene electronics.

High-Performance Top-Gated Graphene-Nanoribbon Transistors Using Zirconium Oxide Nanowires as High-Dielectric-Constant Gate Dielectrics

Graphene has attracted a great deal of interest in the past several years.[1–5] New physics has been predicted and observed, such as ultrahigh carrier mobility,[6] electron-hole symmetry and quantum hall effect,[2, 4, 7–9] and the strong suppression of weak localization.[10–12] For mainstream logic application, graphene nanoribbons (GNRs), as thin strips of graphene or unrolled carbon nanotubes, are predicted to be semiconducting due to edge effects and quantum confinement.[13–15] Recent experimental studies have also demonstrated that GNRs can effectively function as a semiconducting channel for room-temperature field-effect transistors.[16–22] By varying the width of GNRs at selected points, it is also possible to create graphene quantum dots within a GNR for single electron transistors.[23] These studies represent important advances in GNR based electronics. However, most of the efforts to date employ a silicon substrate as a global back gate and silicon oxide as the gate dielectrics. While such a device has led to many interesting scientific discoveries, it will be of limited use for practical applications due to the high gate switching voltage required and the inability to independently address multiple units on the same chip.[17, 20, 21] Top-gated devices with high-k dielectrics can significantly reduce the required switching voltage and allow independently addressable device arrays and functional circuits, and therefore are of significant interest.

Composition tuning the upconversion emission in NaYF4:Yb/Tm hexaplate nanocrystals

Single crystal hexagonal NaYF4:Yb/Tm nanocrystals have been synthesized with uniform size, morphology and controlled chemical composition. Spectroscopic studies show that these nanocrystals exhibit strong energy upconversion emission when excited with a 980 nm diode laser, with two primary emission peaks centered around 452 nm and 476 nm. Importantly, the overall and relative emission intensity at these wavelengths can be readily tuned by controlling the concentration of the trivalent rare earth element dopants at the beginning of the synthesis which has been confirmed by EDX for the first time. Through systematic studies, the optimum rare earth ion doping concentration can be determined for the strongest emission intensity at the selected peak(s). Confocal microscopy studies show that the upconversion emission from individual NCs can be readily visualized. These studies demonstrate a rational approach for fine tuning the upconversion properties in rare-earth doped nanostructures and can broadly impact areas ranging from energy harvesting, energy conversion to biomedical imaging and therapeutics.

Detection of spin polarized carrier in silicon nanowire with single crystal MnSi as magnetic contacts.

We report the formation of single crystal MnSi nanowires, MnSi/Si/MnSi nanowire heterostructures, to study the spin transport in silicon nanostructure. Scanning electron microscopy studies show that silicon nanowires can be converted into single crystal MnSi nanowires through controlled solid-state reaction. High-resolution transmission electron microscope studies show that MnSi/Si/MnSi heterostructures have clean, atomically sharp interfaces with an epitaxial relationship of Si[311]//MnSi[120] and Si(345)//MnSi(214). Magnetoresistance (MR) studies show that the single crystal MnSi nanowire exhibits metallic behavior with paramagnetic to ferromagnetic transition temperature of 29.7 K and a negative MR up to 1.8% at low temperature. Furthermore, using single crystal MnSi/p-Si/MnSi nanowire heterostructures, we have studied carrier tunneling via the Schottky barrier and spin polarized carrier transport in the silicon nanodevices.

Growth of nickel silicides in Si and Si/SiOx core/shell nanowires.

We exploited the oxide shell structure to explore the structure confinement effect on the nickel silicide growth in one-dimensional nanowire template. The oxide confinement structure is similar to the contact structure (via hole) in the thin film system or nanodevices passivated by oxide or nitride film. Silicon nanowires in direct contact with nickel pads transform into two phases of nickel silicides, Ni31Si12 and NiSi2, after one-step annealing at 550 °C. In a bare Si nanowire during the annealing process, NiSi2 grows initially through the nanowire, followed by the transformation of NiSi2 into the nickel-rich phase, Ni31Si12 starting from near the nickel pad. Ni31Si12 is also observed under the nickel pads. Although the same phase transformations of Si to nickel silicides are observed in nanowires with oxide confinement structure, the growth rate of nickel silicides, Ni31Si12 and NiSi2, is retarded dramatically. With increasing oxide thickness from 5 to 50 nm, the retarding effect of the Ni31Si12 growth and the annihilation of Ni2Si into the oxide confined-Si is clearly observed. Ni31Si12 and Ni2Si phases are limited to grow into the Si/SiOx core-shell nanowire as the shell thickness reaches 50 nm. It is experimental evidence that phase transformation is influenced by the stressed structure at nanoscale.