Hans-Joachim L. Gossmann

High efficiency selective emitter enabled through patterned ion implantation

Selective emitter cell architectures offer the opportunity of improved cell efficiency over standard cell architectures through improved blue response, reduced saturation current and lower contact resistance. However, few selective emitter cell concepts have been successfully adopted into high volume manufacturing, often due to the associated increase in process complexity and cost. This paper demonstrates that patterned ion implantation provides a roadmap to lower PV module and system

Enhancing tensile stress and source/drain activation with Si:C with innovations in ion implant and millisecond laser spike annealing

/Wp costs through improved cell efficiency and reduced manufacturing cost. Ion implanted cell efficiency improvements, which can be up to +1% absolute, are a result of not only the selective emitter cell architecture, but also improved emitter quality, oxide passivation and increased light collection area through the elimination of laser edge isolation. Manufacturing cost reductions result from reduced processing steps and improved process uniformity and cell binning.

Finfet and gate-all-around device design and performance/yield optimization

Strain engineering has become a workhorse in increasing charge carrier mobility to boost performance for sub-45nm CMOS logic technologies. While pFET transistors with embedded Si1−xGex layers in the S/D region have been widely employed to induce compressive strain in the silicon channel, nFET transistors have mostly depended on either tensile liners or stress memorization techniques (SMT) to introduce tensile strain. Recently, there have been reports on the use of Si:C in the nFET S/D enhancing transistor performance. In this paper we discuss results from novel ion implantation schemes employed to maximize carbon incorporation and to achieve defect free, strained Si:C layers. In addition, high activation of the dopant is maintained even in the presence of relatively high carbon incorporation. Several anneal techniques including SPE anneal, spike RTP, and laser spike anneals have been used to optimize carbon incorporation, strain and activation. Results from these different anneal techniques will be compared and discussed.

“Abnormal” angle response curves of TW/Rs for near zero tilt and high tilt channeling implants

The three-dimensional (3D) nature of Fin-, Nanowire-, or Gata-All-Around-FETs raises a host of unique challenges to device design and optimization. The sensitivity of a FinFETs threshold voltage (Vth) to the Vth-implant is much lower than in a planar FET but can be improved by 5× through a change in the integration flow (“Well-Implant-Before-STI-Recess”). There still is a Halo implant in a FinFET that is analogous to the Halo implant in planar devices used for device-performance tuning. Unique to FinFETs is a 2nd “Halo” implant, which is effective for Vth adjustment. A Source-Drain-Extension (SDE) implant is instrumental for control of recess-spacer/recess-etch variability.

Device and process design of leading edge transistors for performance and yield

Angle control has been widely accepted as the key requirement for ion implantation in semiconductor device processing. From an ion implanter point of view, the incident ion direction should be measured and corrected by suitable techniques, such as XP-VPS for the VIISta implanter platform, to ensure precision ion placement in device structures. So called V-curves have been adopted to generate the wafer-based calibration using channeling effects as the Si lattice steer ions into a channeling direction. Thermal Wave (TW) or sheet resistance (Rs) can be used to determine the minimum of the angle response curve. Normally it is expected that the TW and Rs have their respective minima at identical angles. However, the TW and Rs response to the angle variations does depend on factors such as implant species, dose, and wafer temperature. Implant damage accumulation effects have to be considered for data interpretation especially for some “abnormal” V-curve data. In this paper we will discuss some observed “abnorma...

Process characterization for hydrogen and helium implantation

The three-dimensional (3D) nature and continued dimensional scaling of Fin-, Nanowire-, and Gate-All-Around-FETs raise a host of unique challenges to device and process design that impact both performance and yield. We highlight selected technology challenges and solutions, specifically doping requirements for isolation, SD/E, and contact, as well as a new advanced planarization technique.

Fabricating high efficiency solar cells with high sheet resistance emitters by ion implantation and contact resistance modeling

Implantation of light ion species, such as Hydrogen and Helium, is widely used to modify silicon electronic properties by adjustment of charge carrier lifetime. Hydrogen-related donors can also be induced in great depth with MeV implants especially for power device applications. However, the radiation related safety concerns require the Hydrogen be used separately from other dopant species normally used in semiconductor manufacturing process. For implanters only equipped with Hydrogen, Helium, or Argon, the implantation process is uniquely challenging to qualify, especially for fabs without ThermaWave or other similar metrology tools. In this paper, we will discuss the characterization of Hydrogen and Helium using double implant technology for angle verification and SPC purpose. Also, TCAD simulation and SRIM studies are used to explain observed multiple Hydrogen peaks for near zero tilt implant profiles.

PIN diode steering element formation for 3D X-bar memory

We present improvements in c-Si solar cell performance for high sheet resistance (R_sheet) emitters fabricated by ion implantation. We have investigated the effect of sheet resistance (60-115 Ω/sq) on cell efficiency (CE) and also evaluated the effect of dopant profile shape on the contact resistance for the ion implanted emitters. High efficiency cells, with average CE>19.3%, can be achieved with ion implanted high R_sheet emitters (60-90 Ω/sq) using commercially available screen printed Ag paste. It is to be noted that the best results were obtained for those cells with emitter R_sheet ~ 70-75 Ω/sq, as the cell performance is limited by the FF, namely front contact resistance (R_c) for emitters with R_sheet > 75 Ω/sq. To better understand the effect of emitter R_sheet and the dopant profile on contact resistance we have used VSEs bottom-up physics-based Technology Computer-Aided Design (TCAD) model to simulate these experimental results. We found that the traditional model of evaluating R_c using the phosphorus surface concentration (N_s) does not accurately predict the increase in R_c and consequently the loss in FF for high R_sheet emitters. We propose an alternative approach to model R_c where the contact depth and its associated dopant concentration (N_d) is employed to calculate R_c. This contact depth is not necessarily zero and may lie below the original Si surface. Our simulated results show that the use of N_d at a depth of the order of 10s of nm below the Si surface leads to better agreement between the experimental and simulated R_series, FF and CE than assuming that the contact is made with Si at the original wafer surface. The implications of these findings with regards to emitter profile engineering via ion implantation and formulation of new pastes to lower R_c of high R_sheet emitters are discussed.

Precision ion implantation: A critical tool for advanced device processing

3D Crossbar (X-Bar) memory architecture is emerging as a strong candidate to enable continuing scaling of non-volatile memories in the post 2D floating gate NAND era. One of the key elements of the X-Bar architecture is a steering element which is required for addressing individual memory cells. Metal oxide ReRAM cells allow operation in unipolar mode where the vertical PIN diode could be used as a steering element. PIN diode steering elements in the X-Bar architecture must concurrently satisfy several challenging requirements: (i) >3MA/cm2 forward current, (ii) > 105 ratio of forward to reverse current, (iii) >3V reverse breakdown voltage. All these characteristics must be achieved in sub-100nm tall diode pillars and less than 20nm in size as dictated by sub-3x 3D X-BAR stack integration requirements. In this paper we report results of the development of an ion implantation process for PIN diodes formation with the above characteristic and demonstrate its scalability down to 50nm pillar diode heights.

Benefits of Zero Degree Single Wafer High Energy Implants for Advanced Semiconductor Device Fabrication

The scaling requirements of device technologies beyond 100 nm can only be satisfied by careful thermal process and defect engineering. We will demonstrate the need for precision ion implantation by focusing on three areas: (1) Junction Formation: Thermal processes trend to ultimately diffusion-less anneals such as laser or flash annealing. As a consequence, the final dopant distribution is more and more dominated by the as-implanted one, which makes implant angle precision imperative. Using TCAD simulations we analyze implant precision requirements for 32 nm half-pitch high-performance logic. A Pareto chart of process variables and their impact on transistor Idsat is developed. (2) Well Formation: Changing the implant angles during well formation to 0° results in improved STI isolation or alternatively in significant die-size reduction. Additionally, channeling implants produce less defects in the surface region leading to a reduction in leakage. Using TCAD simulations of a 80 nm DRAM technology we analyze both aspects quantitatively. (3) Elimination of Residual Damage After Diffusion-Less Anneal: We present results of two techniques designed to eliminate residual damage without the need for a post-anneal thermal process step. Both methods rely on supplementing and/or enhancing amorphization during implantation.